#170 wishbone example now set dBusCmdMasterPipe

2021-08-24 23:24:22 +02:00 · 2021-08-24 23:24:22 +02:00 · 5c7e4a0294
parent 3deeab42fd
commit 5c7e4a0294
1 changed files with 1 additions and 0 deletions
--- a/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
+++ b/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
@ -64,6 +64,7 @@ object VexRiscvCachedWishboneForSim{
              catchIllegal      = true,
              catchUnaligned    = true
            ),
+            dBusCmdMasterPipe = true, //required for wishbone
            memoryTranslatorPortConfig = null
            //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
            //              portTlbSize = 6