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RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot

This commit is contained in:
Charles Papon 2019-11-01 16:24:07 +01:00
parent b4c75d4898
commit bd2787b562
1 changed files with 5 additions and 0 deletions
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5
src/main/scala/vexriscv/plugin/RegFilePlugin.scala
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@ -96,6 +96,11 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
regFileWrite.address := U(shadowPrefix(output(INSTRUCTION)(rdRange))) regFileWrite.address := U(shadowPrefix(output(INSTRUCTION)(rdRange)))
regFileWrite.data := output(REGFILE_WRITE_DATA) regFileWrite.data := output(REGFILE_WRITE_DATA)
//Ensure no boot glitches modify X0
if(!x0Init && zeroBoot) when(regFileWrite.address === 0){
regFileWrite.valid := False
}
//CPU will initialise constant register zero in the first cycle //CPU will initialise constant register zero in the first cycle
if(x0Init) { if(x0Init) {
val boot = RegNext(False) init (True) val boot = RegNext(False) init (True)