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Add JTAG tunnel without TAP in EmbeddedRiscvJtag

This commit is contained in:
Craig Bishop 2024-08-26 17:21:42 -07:00
parent 2073047272
commit bd7c4c3281
1 changed files with 11 additions and 1 deletions
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12
src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
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@ -14,6 +14,7 @@ import vexriscv._
class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
var debugCd : ClockDomain = null,
var jtagCd : ClockDomain = null,
var withTap : Boolean = true,
var withTunneling : Boolean = false
) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
@ -61,7 +62,7 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
dm.io.ctrl <> logic.io.bus
logic.io.jtag <> jtag
}
val dmiTunneled = if(withTap && withTunneling) new Area {
val dmiTunneledWithTap = if(withTap && withTunneling) new Area {
val logic = DebugTransportModuleJtagTapWithTunnel(
p.copy(addressWidth = 7),
debugCd = ClockDomain.current
@ -69,6 +70,15 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
dm.io.ctrl <> logic.io.bus
logic.io.jtag <> jtag
}
val dmiTunneledNoTap = if (!withTap && withTunneling) new Area {
val logic = DebugTransportModuleTunneled(
p.copy(addressWidth = 7),
debugCd = ClockDomain.current,
jtagCd = jtagCd
)
logic.io.instruction <> jtagInstruction
dm.io.ctrl <> logic.io.bus
}
val privBus = pipeline.service(classOf[CsrPlugin]).debugBus.setAsDirectionLess()
privBus <> dm.io.harts(0)