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Add HexTools and add a Briey main which load the ram

This commit is contained in:
Dolu1990 2018-04-26 10:27:39 +02:00
parent cfc324aa0f
commit bdcf3f6234
2 changed files with 54 additions and 33 deletions
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15
src/main/scala/vexriscv/demo/Briey.scala
View File

@ -389,6 +389,21 @@ object Briey{
}
}
//DE1-SoC with memory init
object BrieyWithMemoryInit{
def main(args: Array[String]) {
val config = SpinalConfig()
config.generateVerilog({
val toplevel = new Briey(BrieyConfig.default)
toplevel.axi.vgaCtrl.vga.ctrl.io.error.addAttribute(Verilator.public)
toplevel.axi.vgaCtrl.vga.ctrl.io.frameStart.addAttribute(Verilator.public)
HexTools.initRam(toplevel.axi.ram.ram, "src/main/ressource/hex/muraxDemo.hex", 0x80000000l)
toplevel
})
}
}
//DE0-Nano
object BrieyDe0Nano{
def main(args: Array[String]) {

48
src/main/scala/vexriscv/demo/MuraxUtiles.scala
View File

@ -73,25 +73,7 @@ class MuraxMasterArbiter(simpleBusConfig : SimpleBusConfig) extends Component{
io.dBus.rsp.error := False
}
class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
val io = new Bundle{
val bus = slave(SimpleBus(simpleBusConfig))
}
val ram = Mem(Bits(32 bits), onChipRamSize / 4)
io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.wr) init(False)
io.bus.rsp.data := ram.readWriteSync(
address = (io.bus.cmd.address >> 2).resized,
data = io.bus.cmd.data,
enable = io.bus.cmd.valid,
write = io.bus.cmd.wr,
mask = io.bus.cmd.mask
)
io.bus.cmd.ready := True
if(onChipRamHexFile != null){
object HexTools{
def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={
import scala.io.Source
def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
@ -119,15 +101,39 @@ class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpl
}
}
def initRam[T <: Data](ram : Mem[T], onChipRamHexFile : String, ramOffset : BigInt): Unit ={
val initContent = Array.fill[BigInt](ram.wordCount)(0)
readHexFile(onChipRamHexFile,(address,data) => {
val addressWithoutOffset = address + Int.MinValue
HexTools.readHexFile(onChipRamHexFile,(address,data) => {
val addressWithoutOffset = (address - ramOffset).toInt
initContent(addressWithoutOffset >> 2) |= BigInt(data) << ((addressWithoutOffset & 3)*8)
})
ram.initBigInt(initContent)
}
}
class MuraxSimpleBusRam(onChipRamSize : BigInt, onChipRamHexFile : String, simpleBusConfig : SimpleBusConfig) extends Component{
val io = new Bundle{
val bus = slave(SimpleBus(simpleBusConfig))
}
val ram = Mem(Bits(32 bits), onChipRamSize / 4)
io.bus.rsp.valid := RegNext(io.bus.cmd.fire && !io.bus.cmd.wr) init(False)
io.bus.rsp.data := ram.readWriteSync(
address = (io.bus.cmd.address >> 2).resized,
data = io.bus.cmd.data,
enable = io.bus.cmd.valid,
write = io.bus.cmd.wr,
mask = io.bus.cmd.mask
)
io.bus.cmd.ready := True
if(onChipRamHexFile != null){
HexTools.initRam(ram, onChipRamHexFile, 0x80000000l)
}
}
class MuraxSimpleBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, simpleBusConfig : SimpleBusConfig) extends Component{
assert(apb3Config.dataWidth == simpleBusConfig.dataWidth)