Add GenFullWithTcmIntegrated example
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@ -72,7 +72,7 @@ This repository hosts a RISC-V implementation written in SpinalHDL. Here are som
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- Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv)
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- Linux compatible (SoC : https://github.com/enjoy-digital/linux-on-litex-vexriscv)
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- Zephyr compatible
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- Zephyr compatible
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- [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)
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- [FreeRTOS port](https://github.com/Dolu1990/FreeRTOS-RISCV)
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- Support tightly coupled memory on I$ D$ (see GenFullWithTcm)
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- Support tightly coupled memory on I$ D$ (see GenFullWithTcm / GenFullWithTcmIntegrated)
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The hardware description of this CPU is done by using a very software oriented approach
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The hardware description of this CPU is done by using a very software oriented approach
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(without any overhead in the generated hardware). Here is a list of software concepts used:
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(without any overhead in the generated hardware). Here is a list of software concepts used:
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@ -0,0 +1,97 @@
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package vexriscv.demo
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import spinal.core._
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import spinal.lib.bus.misc.SizeMapping
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import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
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import vexriscv.plugin._
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import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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/**
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* this example integrate the tightly coupled memory directly inside VexRiscv
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* by using the IBusDBusCachedTightlyCoupledRam plugin
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*/
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object GenFullWithTcmIntegrated extends App{
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def config = VexRiscvConfig(
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plugins = List(
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new IBusDBusCachedTightlyCoupledRam(
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mapping = SizeMapping(0x20000000, 0x1000)
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),
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new IBusCachedPlugin(
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prediction = DYNAMIC,
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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asyncTagMemory = false,
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twoCycleRam = true,
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twoCycleCache = true
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 4
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)
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),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true
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),
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memoryTranslatorPortConfig = MmuPortConfig(
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portTlbSize = 6
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)
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),
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new MmuPlugin(
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin(
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separatedAddSub = false,
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executeInsertion = true
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),
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new FullBarrelShifterPlugin,
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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bypassWriteBack = true,
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bypassWriteBackBuffer = true,
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pessimisticUseSrc = false,
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pessimisticWriteRegFile = false,
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pessimisticAddressMatch = false
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),
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new MulPlugin,
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new DivPlugin,
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new CsrPlugin(CsrPluginConfig.small(0x80000020l)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = false,
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catchAddressMisaligned = true
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),
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new YamlPlugin("cpu0.yaml")
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)
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)
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def cpu() = new VexRiscv(
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config
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)
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SpinalVerilog(cpu())
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}
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