Merge branch 'dev'
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commit
05df181257
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@ -680,7 +680,8 @@ class IBusDBusCachedTightlyCoupledRam(mapping : SizeMapping, withIBus : Boolean
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address = (dbus.address >> 2).resized,
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data = dbus.write_data,
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enable = dbus.enable,
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write = dbus.write_enable
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write = dbus.write_enable,
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mask = dbus.write_mask
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)
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}
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val i = withIBus generate new Area {
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