update ScopeProperty usages

src/main/scala/vexriscv/Stage.scala

@@ -15,10 +15,10 @@ class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with
 class Stage() extends Area{
   def outsideCondScope[T](that : => T) : T = {
     val body = Component.current.dslBody  // Get the head of the current component symboles tree (AST in other words)
-    body.push()                           // Now all access to the SpinalHDL API will be append to it (instead of the current context)
+    val ctx = body.push()                           // Now all access to the SpinalHDL API will be append to it (instead of the current context)
     val swapContext = body.swap()         // Empty the symbole tree (but keep a reference to the old content)
     val ret = that                        // Execute the block of code (will be added to the recently empty body)
-    body.pop()                            // Restore the original context in which this function was called
+    ctx.restore()                            // Restore the original context in which this function was called
     swapContext.appendBack()              // append the original symboles tree to the modified body
     ret                                   // return the value returned by that
   }

src/main/scala/vexriscv/demo/Briey.scala

@@ -51,52 +51,56 @@ object BrieyConfig{
       ),
       cpuPlugins = ArrayBuffer(
         new PcManagerSimplePlugin(0x80000000l, false),
-        //          new IBusSimplePlugin(
+        new IBusSimplePlugin(
-        //            interfaceKeepData = false,
-        //            catchAccessFault = true
-        //          ),
-        new IBusCachedPlugin(
           resetVector = 0x80000000l,
-          prediction = STATIC,
+          cmdForkOnSecondStage = false,
-          config = InstructionCacheConfig(
+          cmdForkPersistence = true,
-            cacheSize = 4096,
+          catchAccessFault = true,
-            bytePerLine =32,
+          compressedGen = true
-            wayCount = 1,
+        ),
-            addressWidth = 32,
+//        new IBusCachedPlugin(
-            cpuDataWidth = 32,
+//          resetVector = 0x80000000l,
-            memDataWidth = 32,
+//          prediction = STATIC,
-            catchIllegalAccess = true,
+//          compressedGen = true,
-            catchAccessFault = true,
+//          config = InstructionCacheConfig(
-            asyncTagMemory = false,
+//            cacheSize = 4096,
-            twoCycleRam = true,
+//            bytePerLine =32,
-            twoCycleCache = true
+//            wayCount = 1,
-          )
+//            addressWidth = 32,
+//            cpuDataWidth = 32,
+//            memDataWidth = 32,
+//            catchIllegalAccess = true,
+//            catchAccessFault = true,
+//            asyncTagMemory = false,
+//            twoCycleRam = true,
+//            twoCycleCache = true
+//          )
           //            askMemoryTranslation = true,
           //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
           //              portTlbSize = 4
           //            )
-        ),
+//        ),
-        //                    new DBusSimplePlugin(
+                            new DBusSimplePlugin(
-        //                      catchAddressMisaligned = true,
+                              catchAddressMisaligned = true,
-        //                      catchAccessFault = true
+                              catchAccessFault = true
-        //                    ),
+                            ),
-        new DBusCachedPlugin(
+//        new DBusCachedPlugin(
-          config = new DataCacheConfig(
+//          config = new DataCacheConfig(
-            cacheSize         = 4096,
+//            cacheSize         = 4096,
-            bytePerLine       = 32,
+//            bytePerLine       = 32,
-            wayCount          = 1,
+//            wayCount          = 1,
-            addressWidth      = 32,
+//            addressWidth      = 32,
-            cpuDataWidth      = 32,
+//            cpuDataWidth      = 32,
-            memDataWidth      = 32,
+//            memDataWidth      = 32,
-            catchAccessError  = true,
+//            catchAccessError  = true,
-            catchIllegal      = true,
+//            catchIllegal      = true,
-            catchUnaligned    = true
+//            catchUnaligned    = true
-          ),
+//          ),
-          memoryTranslatorPortConfig = null
+//          memoryTranslatorPortConfig = null
-          //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
+//          //            memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
-          //              portTlbSize = 6
+//          //              portTlbSize = 6
-          //            )
+//          //            )
-        ),
+//        ),
         new StaticMemoryTranslatorPlugin(
           ioRange      = _(31 downto 28) === 0xF
         ),
@@ -104,7 +108,7 @@ object BrieyConfig{
           catchIllegalInstruction = true
         ),
         new RegFilePlugin(
-          regFileReadyKind = plugin.SYNC,
+          regFileReadyKind = plugin.ASYNC,
           zeroBoot = false
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala

@@ -43,9 +43,9 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
   systemCd.setInput(debugCd)
 
 
-  systemCd.outputClockDomain.push()
+  val ctx = systemCd.outputClockDomain.push()
   override def postInitCallback(): VexRiscvSmpClusterBase.this.type = {
-    systemCd.outputClockDomain.pop()
+    ctx.restore()
     this
   }