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CSR unsetRegIfNoAssignement fix 

BranchPlugin doesn't emit the prediction cache when the STATIC setup is used
This commit is contained in:
Dolu1990 2017-11-10 00:59:31 +01:00
parent d6777ae8ec
commit c3a7f4e58c
2 changed files with 5 additions and 5 deletions
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4
src/main/scala/vexriscv/plugin/BranchPlugin.scala
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@ -147,8 +147,8 @@ class BranchPlugin(earlyBranch : Boolean,
import pipeline._ import pipeline._
import pipeline.config._ import pipeline.config._
val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
val historyCacheWrite = historyCache.writePort val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
//Read historyCache //Read historyCache
if(prediction == DYNAMIC) fetch plug new Area{ if(prediction == DYNAMIC) fetch plug new Area{

6
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
//Define CSR registers //Define CSR registers
val misa = new Area{ val misa = new Area{
val base = Reg(UInt(2 bits)) init(U"01") val base = Reg(UInt(2 bits)) init(U"01") unsetRegIfNoAssignement
val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) unsetRegIfNoAssignement
} }
val mtvec = RegInit(U(mtvecInit,xlen bits)) val mtvec = RegInit(U(mtvecInit,xlen bits)) unsetRegIfNoAssignement
val mepc = Reg(UInt(xlen bits)) val mepc = Reg(UInt(xlen bits))
val mstatus = new Area{ val mstatus = new Area{
val MIE, MPIE = RegInit(False) val MIE, MPIE = RegInit(False)