Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

IBusSimplePlugin can now use a Vec based buffer

This commit is contained in:
Dolu1990 2021-10-13 16:26:16 +02:00
parent 97a3c1955b
commit c3c3a94c5d
2 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
View File

@ -266,7 +266,8 @@ object VexRiscvSmpClusterGen {
prediction = NONE,
catchAccessFault = false,
compressedGen = rvc,
busLatencyMin = 2
busLatencyMin = 2,
vecRspBuffer = true
),
if(withDataCache) new DBusCachedPlugin(
dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,

5
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View File

@ -236,7 +236,8 @@ class IBusSimplePlugin( resetVector : BigInt,
val memoryTranslatorPortConfig : Any = null,
relaxPredictorAddress : Boolean = true,
predictionBuffer : Boolean = true,
bigEndian : Boolean = false
bigEndian : Boolean = false,
vecRspBuffer : Boolean = false
) extends IBusFetcherImpl(
resetVector = resetVector,
keepPcPlus4 = keepPcPlus4,
@ -351,7 +352,7 @@ class IBusSimplePlugin( resetVector : BigInt,
//Manage flush for iBus transactions in flight
val rspBuffer = new Area {
val output = Stream(IBusSimpleRsp())
val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
val c = new StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0), useVec = vecRspBuffer)
val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
when(iBusRsp.flush) {