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https://github.com/SpinalHDL/VexRiscv.git
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IBusSimplePlugin can now use a Vec based buffer
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parent
97a3c1955b
commit
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2 changed files with 5 additions and 3 deletions
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@ -266,7 +266,8 @@ object VexRiscvSmpClusterGen {
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prediction = NONE,
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prediction = NONE,
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catchAccessFault = false,
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catchAccessFault = false,
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compressedGen = rvc,
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compressedGen = rvc,
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busLatencyMin = 2
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busLatencyMin = 2,
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vecRspBuffer = true
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),
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),
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if(withDataCache) new DBusCachedPlugin(
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if(withDataCache) new DBusCachedPlugin(
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dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,
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dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,
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@ -236,7 +236,8 @@ class IBusSimplePlugin( resetVector : BigInt,
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val memoryTranslatorPortConfig : Any = null,
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val memoryTranslatorPortConfig : Any = null,
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relaxPredictorAddress : Boolean = true,
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relaxPredictorAddress : Boolean = true,
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predictionBuffer : Boolean = true,
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predictionBuffer : Boolean = true,
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bigEndian : Boolean = false
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bigEndian : Boolean = false,
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vecRspBuffer : Boolean = false
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) extends IBusFetcherImpl(
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) extends IBusFetcherImpl(
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resetVector = resetVector,
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resetVector = resetVector,
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keepPcPlus4 = keepPcPlus4,
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keepPcPlus4 = keepPcPlus4,
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@ -351,7 +352,7 @@ class IBusSimplePlugin( resetVector : BigInt,
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//Manage flush for iBus transactions in flight
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//Manage flush for iBus transactions in flight
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val rspBuffer = new Area {
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val rspBuffer = new Area {
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val output = Stream(IBusSimpleRsp())
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val output = Stream(IBusSimpleRsp())
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val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
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val c = new StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0), useVec = vecRspBuffer)
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
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discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
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when(iBusRsp.flush) {
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when(iBusRsp.flush) {
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