Now able to catch missaligned instruction/data addresses
Modify arbitration with an flushAll + isFlushed
This commit is contained in:
parent
4000191966
commit
c5520656e5
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@ -94,7 +94,7 @@ trait Pipeline {
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inputDefault := stage.inserts(key)
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} else {
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val stageBefore = stages(stageIndex - 1)
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inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck || stage.arbitration.removeIt)
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inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck)
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}
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}
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}
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@ -102,8 +102,9 @@ trait Pipeline {
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//Arbitration
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for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)) {
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stage.arbitration.isFlushed := stages.drop(stageIndex).map(_.arbitration.flushAll).orR
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if(!unremovableStages.contains(stage))
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stage.arbitration.removeIt setWhen stages.drop(stageIndex).map(_.arbitration.flushIt).orR
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stage.arbitration.removeIt setWhen stage.arbitration.isFlushed
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else
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assert(stage.arbitration.removeIt === False,"removeIt should never be asserted on this stage")
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@ -10,7 +10,11 @@ object NONE extends BranchPrediction
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object STATIC extends BranchPrediction
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object DYNAMIC extends BranchPrediction
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class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRamSizeLog2 : Int = 10,historyWidth : Int = 2) extends Plugin[VexRiscv]{
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class BranchPlugin(earlyBranch : Boolean,
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unalignedExceptionGen : Boolean,
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prediction : BranchPrediction,
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historyRamSizeLog2 : Int = 10,
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historyWidth : Int = 2) extends Plugin[VexRiscv]{
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object BranchCtrlEnum extends SpinalEnum(binarySequential){
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val INC,B,JAL,JALR = newElement()
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}
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@ -22,6 +26,8 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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var jumpInterface : Flow[UInt] = null
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var predictionJumpInterface : Flow[UInt] = null
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var predictionExceptionPort : Flow[ExceptionCause] = null
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var branchExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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@ -50,7 +56,7 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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decoderService.addDefault(BRANCH_CTRL, BranchCtrlEnum.INC)
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decoderService.add(List(
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JAL -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL , ALU_CTRL -> AluCtrlEnum.ADD_SUB)),
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JAL -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL, ALU_CTRL -> AluCtrlEnum.ADD_SUB)),
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JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, ALU_CTRL -> AluCtrlEnum.ADD_SUB, REG1_USE -> True)),
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BEQ -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
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BNE -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
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@ -62,7 +68,15 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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val pcManagerService = pipeline.service(classOf[JumpService])
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jumpInterface = pcManagerService.createJumpInterface(pipeline.execute)
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if(prediction != NONE) predictionJumpInterface = pcManagerService.createJumpInterface(pipeline.decode)
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if (prediction != NONE)
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predictionJumpInterface = pcManagerService.createJumpInterface(pipeline.decode)
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if (unalignedExceptionGen) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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branchExceptionPort = exceptionService.newExceptionPort(if (earlyBranch) pipeline.execute else pipeline.memory)
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if (prediction != NONE)
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predictionExceptionPort = exceptionService.newExceptionPort(pipeline.decode)
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}
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}
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override def build(pipeline: VexRiscv): Unit = prediction match {
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@ -112,7 +126,12 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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stages(indexOf(branchStage) - 1).arbitration.flushIt := True
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(unalignedExceptionGen) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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}
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}
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}
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@ -157,7 +176,12 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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predictionJumpInterface.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isFiring //TODO OH Doublon de priorité
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predictionJumpInterface.payload := input(PC) + ((input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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when(predictionJumpInterface.valid) {
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fetch.arbitration.flushIt := True
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fetch.arbitration.flushAll := True
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}
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if(unalignedExceptionGen) {
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predictionExceptionPort.valid := input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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predictionExceptionPort.code := 0
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}
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}
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@ -207,7 +231,12 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
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jumpInterface.payload := input(BRANCH_CALC)
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when(jumpInterface.valid) {
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stages(indexOf(branchStage) - 1).arbitration.flushIt := True
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stages(indexOf(branchStage) - 1).arbitration.flushAll := True
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}
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if(unalignedExceptionGen) {
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branchExceptionPort.valid := arbitration.isValid && input(BRANCH_DO) && jumpInterface.payload(1 downto 0) =/= 0
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branchExceptionPort.code := 0
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}
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}
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@ -16,7 +16,7 @@ case class DBusSimpleRsp() extends Bundle{
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val data = Bits(32 bit)
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}
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class DBusSimplePlugin extends Plugin[VexRiscv]{
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class DBusSimplePlugin(unalignedExceptionGen : Boolean) extends Plugin[VexRiscv]{
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var dCmd : Stream[DBusSimpleCmd] = null
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var dRsp : DBusSimpleRsp = null
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@ -30,7 +30,7 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
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object MEMORY_READ_DATA extends Stageable(Bits(32 bits))
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object MEMORY_ADDRESS_LOW extends Stageable(UInt(2 bits))
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var executeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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@ -71,9 +71,10 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
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SW -> (storeActions)
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))
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// val exceptionService = pipeline.service(classOf[ExceptionService])
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// executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
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if(unalignedExceptionGen) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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executeExceptionPort = exceptionService.newExceptionPort(pipeline.execute)
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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@ -99,6 +100,12 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
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}
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insert(MEMORY_ADDRESS_LOW) := dCmd.address(1 downto 0)
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if(unalignedExceptionGen){
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executeExceptionPort.code := (dCmd.wr ? U(6) | U(4)).resized
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executeExceptionPort.valid := (arbitration.isValid && input(MEMORY_ENABLE)
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&& ((dCmd.size === 2 && dCmd.address(1 downto 0) =/= 0) || (dCmd.size === 1 && dCmd.address(0 downto 0) =/= 0)))
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}
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}
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//Collect dRsp read responses
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@ -17,6 +17,10 @@ class IBusSimplePlugin(interfaceKeepData : Boolean) extends Plugin[VexRiscv]{
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var iCmd : Stream[IBusSimpleCmd] = null
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var iRsp : IBusSimpleRsp = null
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override def setup(pipeline: VexRiscv): Unit = {
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pipeline.unremovableStages += pipeline.prefetch
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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@ -89,9 +89,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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}
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object ENV_CTRL extends Stageable(EnvCtrlEnum())
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object EXCEPTION extends Stageable(Bool)
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// object EXCEPTION extends Stageable(Bool)
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object IS_CSR extends Stageable(Bool)
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object EXCEPTION_CAUSE extends Stageable(ExceptionCause())
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// object EXCEPTION_CAUSE extends Stageable(ExceptionCause())
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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@ -241,8 +241,12 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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//Aggregate all exception port and remove required instructions
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val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
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val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
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val pipelineHasException = stages.drop(firstStageIndexWithExceptionPort).map(s => s.arbitration.isValid && s.input(EXCEPTION)).orR
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decode.arbitration.haltIt setWhen(pipelineHasException)
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val exceptionValids = Vec(Bool,stages.length)
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val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length)
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val exceptionContext = Reg(ExceptionCause())
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val pipelineHasException = exceptionValids.orR
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pipelineLiberator.enable setWhen(pipelineHasException)
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val groupedByStage = exceptionPortsInfos.map(_.stage).distinct.map(s => {
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assert(s != writeBack)
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@ -260,27 +264,40 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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}
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ExceptionPortInfo(stagePort,s)
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})
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage))
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sortedByStage.head.stage.insert(EXCEPTION) := False
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sortedByStage.head.stage.insert(EXCEPTION_CAUSE).assignDontCare()
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for(portInfo <- sortedByStage; port = portInfo.port ; stage = portInfo.stage){
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when(port.valid){
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stages(indexOf(stage) - 1).arbitration.flushIt := True
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stage.input(EXCEPTION) := True
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stage.input(EXCEPTION_CAUSE) := port.payload
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val sortedByStage = groupedByStage.sortWith((a, b) => pipeline.indexOf(a.stage) < pipeline.indexOf(b.stage))
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exceptionValids := exceptionValidsRegs
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for(portInfo <- sortedByStage; port = portInfo.port ; stage = portInfo.stage; stageId = indexOf(portInfo.stage)) {
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when(port.valid) {
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stages(indexOf(stage) - 1).arbitration.flushAll := True
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stage.arbitration.removeIt := True
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exceptionValids(stageId) := True
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exceptionContext := port.payload
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}
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}
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for(stageId <- firstStageIndexWithExceptionPort until stages.length; stage = stages(stageId) ){
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when(stage.arbitration.isFlushed){
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exceptionValids(stageId) := False
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}
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when(!stage.arbitration.isStuck){
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exceptionValidsRegs(stageId) := (if(stageId != firstStageIndexWithExceptionPort) exceptionValids(stageId-1) else False)
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}otherwise{
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exceptionValidsRegs(stageId) := exceptionValids(stageId)
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}
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}
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} else null
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val interrupt = ((mip.MSIP && mie.MSIE) || (mip.MEIP && mie.MEIE) || (mip.MTIP && mie.MTIE)) && mstatus.MIE
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val exception = if(exceptionPortsInfos.nonEmpty) writeBack.arbitration.isValid && writeBack.input(EXCEPTION) else False
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val exception = if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionValids.last else False
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val writeBackWfi = if(wfiGen) writeBack.arbitration.isValid && writeBack.input(ENV_CTRL) === EnvCtrlEnum.WFI else False
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//Interrupt/Exception entry logic
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pipelineLiberator.enable setWhen interrupt
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pipelineLiberator.enable setWhen(interrupt)
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when(exception || (interrupt && pipelineLiberator.done)){
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jumpInterface.valid := True
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jumpInterface.payload := mtvec
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@ -294,7 +311,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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mcause.interrupt := interrupt
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mcause.exceptionCode := interrupt.mux(
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True -> ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))),
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False -> (if(exceptionPortCtrl != null) writeBack.input(EXCEPTION_CAUSE).exceptionCode else U(0))
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False -> (if(exceptionPortCtrl != null) exceptionPortCtrl.exceptionContext.code else U(0))
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)
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}
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@ -303,21 +320,21 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
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when(memory.arbitration.isFiring && memory.input(ENV_CTRL) === EnvCtrlEnum.MRET){
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jumpInterface.valid := True
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jumpInterface.payload := mepc
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execute.arbitration.flushIt := True
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execute.arbitration.flushAll := True
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mstatus.MIE := mstatus.MPIE
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}
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//Manage ECALL instructions
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if(ecallGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.ECALL){
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pluginExceptionPort.valid := True
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pluginExceptionPort.exceptionCode := 11
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pluginExceptionPort.code := 11
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}
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//Manage WFI instructions
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if(wfiGen) when(execute.arbitration.isValid && execute.input(ENV_CTRL) === EnvCtrlEnum.WFI){
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when(!interrupt){
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execute.arbitration.haltIt := True
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decode.arbitration.flushIt := True
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decode.arbitration.flushAll := True
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}
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}
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@ -1,12 +1,12 @@
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package SpinalRiscv.Plugin
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import SpinalRiscv.{JumpService, Stage, VexRiscv}
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import SpinalRiscv._
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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class PcManagerSimplePlugin(resetVector : BigInt,fastPcCalculation : Boolean) extends Plugin[VexRiscv] with JumpService{
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class PcManagerSimplePlugin(resetVector : BigInt, fastPcCalculation : Boolean) extends Plugin[VexRiscv] with JumpService{
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//FetchService interface
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@ -17,6 +17,7 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastPcCalculation : Boolean) ex
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jumpInfos += JumpInfo(interface,stage)
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interface
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}
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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pipeline.unremovableStages += pipeline.prefetch
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@ -9,7 +9,7 @@ trait RegFileReadKind
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object ASYNC extends RegFileReadKind
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object SYNC extends RegFileReadKind
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class RegFilePlugin(regFileReadyKind : RegFileReadKind) extends Plugin[VexRiscv]{
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class RegFilePlugin(regFileReadyKind : RegFileReadKind,zeroBoot : Boolean = false) extends Plugin[VexRiscv]{
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import Riscv._
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override def setup(pipeline: VexRiscv): Unit = {
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@ -25,6 +25,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind) extends Plugin[VexRiscv]
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val global = pipeline plug new Area{
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val regFile = Mem(Bits(32 bits),32) addAttribute("verilator public")
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if(zeroBoot) regFile.init(List.fill(32)(B(0, 32 bits)))
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}
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//Read register file
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@ -14,7 +14,7 @@ trait DecoderService{
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}
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case class ExceptionCause() extends Bundle{
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val exceptionCode = UInt(4 bits)
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val code = UInt(4 bits)
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}
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trait ExceptionService{
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@ -47,9 +47,10 @@ class Stage() extends Area{
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val arbitration = new Area{
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val haltIt = False
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val removeIt = False
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val flushIt = False
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val flushAll = False
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val isValid = RegInit(False)
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val isStuck = Bool
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val isFlushed = Bool
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val isStuckByOthers = Bool
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val isFiring = Bool
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}
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@ -46,8 +46,8 @@ object TopLevel {
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mbadaddrAccess = CsrAccess.READ_WRITE,
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mcycleAccess = CsrAccess.READ_WRITE,
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minstretAccess = CsrAccess.READ_WRITE,
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ecallGen = false,
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wfiGen = false
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ecallGen = true,
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wfiGen = true
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)
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// val csrConfig = MachineCsrConfig(
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@ -69,30 +69,35 @@ object TopLevel {
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config.plugins ++= List(
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new PcManagerSimplePlugin(0x00000000l, false),
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new IBusSimplePlugin(true),
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new IBusSimplePlugin(
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interfaceKeepData = true
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),
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new DecoderSimplePlugin,
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new RegFilePlugin(Plugin.SYNC),
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new RegFilePlugin(
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regFileReadyKind = Plugin.SYNC,
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zeroBoot = false
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),
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new IntAluPlugin,
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new SrcPlugin,
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new FullBarrielShifterPlugin,
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// new LightShifterPlugin,
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new DBusSimplePlugin,
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// new HazardSimplePlugin(false, true, false, true),
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new DBusSimplePlugin(
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unalignedExceptionGen = true
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),
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new HazardSimplePlugin(true, true, true, true),
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// new HazardSimplePlugin(false, true, false, true),
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// new HazardSimplePlugin(false, false, false, false),
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new MulPlugin,
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new DivPlugin,
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new MachineCsr(csrConfig),
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new BranchPlugin(false, DYNAMIC)
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new BranchPlugin(
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earlyBranch = false,
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unalignedExceptionGen = true,
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prediction = DYNAMIC
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)
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)
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val toplevel = new VexRiscv(config)
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// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
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toplevel
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}
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}
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|
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@ -22,7 +22,7 @@ Arr_1_Glob[8]: 7
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Arr_2_Glob[8][7]: 210
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should be: Number_Of_Runs + 10
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Ptr_Glob->
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Ptr_Comp: 1073809016
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Ptr_Comp: 1073810920
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should be: (implementation-dependent)
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Discr: 0
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should be: 0
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@ -33,7 +33,7 @@ Ptr_Glob->
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Str_Comp: DHRYSTONE PROGRAM, SOME STRING
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should be: DHRYSTONE PROGRAM, SOME STRING
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Next_Ptr_Glob->
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Ptr_Comp: 1073809016
|
||||
Ptr_Comp: 1073810920
|
||||
should be: (implementation-dependent), same as above
|
||||
Discr: 0
|
||||
should be: 0
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,45 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
|
||||
[*] Sat Mar 25 22:06:00 2017
|
||||
[*]
|
||||
[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/dhrystoneO3.vcd"
|
||||
[dumpfile_mtime] "Sat Mar 25 22:05:31 2017"
|
||||
[dumpfile_size] 414222144
|
||||
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/fail.gtkw"
|
||||
[timestart] 60961
|
||||
[size] 1000 600
|
||||
[pos] -1 -1
|
||||
*-7.000000 61271 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] TOP.
|
||||
[sst_width] 201
|
||||
[signals_width] 571
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 155
|
||||
@28
|
||||
TOP.VexRiscv.decode_EXCEPTION
|
||||
TOP.VexRiscv.execute_EXCEPTION
|
||||
TOP.VexRiscv.memory_EXCEPTION
|
||||
TOP.VexRiscv.writeBack_EXCEPTION
|
||||
TOP.VexRiscv.execute_arbitration_isValid
|
||||
TOP.VexRiscv.execute_MEMORY_ENABLE
|
||||
@22
|
||||
TOP.VexRiscv.execute_PC[31:0]
|
||||
TOP.VexRiscv.RegFilePlugin_regFile(8)[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.writeBack_arbitration_isValid
|
||||
@23
|
||||
TOP.VexRiscv.writeBack_PC[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
|
||||
@22
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
|
||||
TOP.VexRiscv.dCmd_payload_address[31:0]
|
||||
TOP.VexRiscv.dCmd_payload_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.dCmd_payload_size[1:0]
|
||||
TOP.VexRiscv.dCmd_payload_wr
|
||||
TOP.VexRiscv.dCmd_ready
|
||||
TOP.VexRiscv.dCmd_valid
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
|
@ -1,5 +1,8 @@
|
|||
#include "VVexRiscv.h"
|
||||
#include "VVexRiscv_VexRiscv.h"
|
||||
#ifdef REF
|
||||
#include "VVexRiscv_RiscvCore.h"
|
||||
#endif
|
||||
#include "verilated.h"
|
||||
#include "verilated_vcd_c.h"
|
||||
#include <stdio.h>
|
||||
|
@ -214,7 +217,12 @@ public:
|
|||
top->clk = 1;
|
||||
|
||||
postReset();
|
||||
|
||||
#ifdef REF
|
||||
if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc;
|
||||
#else
|
||||
if(bootPc != -1) top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = bootPc;
|
||||
#endif
|
||||
|
||||
try {
|
||||
// run simulation for 100 clock periods
|
||||
|
@ -245,11 +253,15 @@ public:
|
|||
|
||||
uint32_t addr = top->dCmd_payload_address;
|
||||
if(top->dCmd_payload_wr){
|
||||
memTraces << (currentTime
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) << " : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
|
||||
) <<
|
||||
#endif
|
||||
" : WRITE mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << top->dCmd_payload_data << endl;
|
||||
for(uint32_t b = 0;b < (1 << top->dCmd_payload_size);b++){
|
||||
uint32_t offset = (addr+b)&0x3;
|
||||
*mem.get(addr + b) = top->dCmd_payload_data >> (offset*8);
|
||||
|
@ -280,11 +292,15 @@ public:
|
|||
case 0xF00FFF48u: dRsp_inst_next = mTimeCmp; break;
|
||||
case 0xF00FFF4Cu: dRsp_inst_next = mTimeCmp >> 32; break;
|
||||
}
|
||||
memTraces << (currentTime
|
||||
memTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
(currentTime
|
||||
#ifdef REF
|
||||
-2
|
||||
#endif
|
||||
) << " : READ mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
|
||||
) <<
|
||||
#endif
|
||||
" : READ mem" << (1 << top->dCmd_payload_size) << "[" << addr << "] = " << dRsp_inst_next << endl;
|
||||
|
||||
}
|
||||
}
|
||||
|
@ -303,7 +319,11 @@ public:
|
|||
if(iStall) top->iCmd_ready = VL_RANDOM_I(1);
|
||||
if(dStall) top->dCmd_ready = VL_RANDOM_I(1);
|
||||
if(top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_valid == 1 && top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address != 0){
|
||||
regTraces << currentTime << " : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
|
||||
regTraces <<
|
||||
#ifdef TRACE_WITH_TIME
|
||||
currentTime <<
|
||||
#endif
|
||||
" : reg[" << (uint32_t)top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_address << "] = " << top->VexRiscv->writeBack_RegFilePlugin_regFileWrite_payload_data << endl;
|
||||
}
|
||||
checks();
|
||||
}
|
||||
|
@ -413,7 +433,7 @@ public:
|
|||
}
|
||||
|
||||
virtual void checks(){
|
||||
if(top->VexRiscv->writeBack_arbitration_isValid == 1 && top->VexRiscv->writeBack_INSTRUCTION == 0x00000073){
|
||||
if(/*top->VexRiscv->writeBack_arbitration_isValid == 1 && */top->VexRiscv->writeBack_INSTRUCTION == 0x00000073){
|
||||
uint32_t code = top->VexRiscv->RegFilePlugin_regFile[28];
|
||||
if((code & 1) == 0){
|
||||
cout << "Wrong error code"<< endl;
|
||||
|
@ -564,15 +584,19 @@ int main(int argc, char **argv, char **env) {
|
|||
for(const string &name : riscvTestDiv){
|
||||
redo(REDO,RiscvTest(name).run();)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CSR
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,8};
|
||||
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5,6,7,0x80000007u ,
|
||||
8,6,9,6,10,4,11,4, 12,13,0,14};
|
||||
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(2e3);)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef DHRYSTONE
|
||||
Dhrystone("dhrystoneO3",true,true).run(1e6);
|
||||
// Dhrystone("dhrystoneO3",false,false).run(0.05e6);
|
||||
Dhrystone("dhrystoneO3",true,true).run(1.1e6);
|
||||
Dhrystone("dhrystoneO3M",true,true).run(0.8e6);
|
||||
Dhrystone("dhrystoneO3M",false,false).run(0.8e6);
|
||||
// Dhrystone("dhrystoneO3ML",false,false).run(8e6);
|
||||
|
@ -580,8 +604,8 @@ int main(int argc, char **argv, char **env) {
|
|||
#endif
|
||||
|
||||
|
||||
#ifdef CSR
|
||||
redo(REDO,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
#ifdef FREE_RTOS
|
||||
redo(1,Workspace("freeRTOS_demo").loadHex("../../resources/hex/freeRTOS_demo.hex")->bootAt(0x80000000u)->run(100e6);)
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
@ -2,7 +2,10 @@ TRACE=no
|
|||
TRACE_START=0
|
||||
CSR=yes
|
||||
DHRYSTONE=yes
|
||||
REDO=5
|
||||
FREE_RTOS=no
|
||||
REDO=10
|
||||
REF=no
|
||||
TRACE_WITH_TIME=no
|
||||
|
||||
ADDCFLAGS += -CFLAGS -DREDO=${REDO}
|
||||
ifeq ($(DHRYSTONE),yes)
|
||||
|
@ -18,7 +21,19 @@ ifeq ($(CSR),yes)
|
|||
ADDCFLAGS += -CFLAGS -DCSR
|
||||
endif
|
||||
|
||||
ifeq ($(TRACE_WITH_TIME),yes)
|
||||
ADDCFLAGS += -CFLAGS -DTRACE_WITH_TIME
|
||||
endif
|
||||
|
||||
ifeq ($(REF),yes)
|
||||
ADDCFLAGS += -CFLAGS -DREF
|
||||
endif
|
||||
|
||||
ADDCFLAGS += -CFLAGS -DTRACE_START=${TRACE_START}
|
||||
ifeq ($(FREE_RTOS),yes)
|
||||
ADDCFLAGS += -CFLAGS -DFREE_RTOS
|
||||
endif
|
||||
|
||||
|
||||
run: compile
|
||||
./obj_dir/VVexRiscv
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,24 +1,30 @@
|
|||
:100000006F00000713000000130000001300000041
|
||||
:100000006F0000091300000013000000130000003F
|
||||
:100010001300000013000000130000001300000094
|
||||
:10002000732E2034930EB0006398CE01F32E10345B
|
||||
:10003000938E4E0073901E34B70E0080938E3E0058
|
||||
:100040006396CE01930E800073B04E34B70E0080DD
|
||||
:10005000938E7E006394CE0173504030B70E0080C3
|
||||
:10006000938EBE006394CE017350403073002030F5
|
||||
:10007000130E100073000000130E20009302800086
|
||||
:1000800073A002309302800073904230930280008C
|
||||
:1000900073A042341300000013000000130000009E
|
||||
:1000A0001300000013000000130000001300000004
|
||||
:1000B00013000000130000001300000013000000F4
|
||||
:1000C00013000000130E30009302000873904230BA
|
||||
:10002000732E2034631E0E00130FC0FFF32E103406
|
||||
:10003000B3FEEE01938E4E0073901E346F00C0012C
|
||||
:10004000B70E0080337FDE0163180F00F32E1034EB
|
||||
:10005000938E4E0073901E34B70E0080938E3E0038
|
||||
:100060006396CE01930E800073B04E34B70E0080BD
|
||||
:10007000938E7E006394CE0173504030B70E0080A3
|
||||
:10008000938EBE006394CE017350403073002030D5
|
||||
:10009000130E100073000000130E20009302800066
|
||||
:1000A00073A002309302800073904230930280006C
|
||||
:1000B00073A042341300000013000000130000007E
|
||||
:1000C00013000000130000001300000013000000E4
|
||||
:1000D00013000000130000001300000013000000D4
|
||||
:1000E000130000001300000013000000130E400076
|
||||
:1000F000B712000093820280739042301300000018
|
||||
:1001000013000000130000001300000013000000A3
|
||||
:100110001300000013000000130E5000B70110F090
|
||||
:10012000938101F403A2010083A241001302F23F74
|
||||
:1001300023A4410023A65100130E600013020008FF
|
||||
:1001400073104230130E700073005010130E8000B5
|
||||
:1000E00013000000130E300093020008739042309A
|
||||
:1000F00013000000130000001300000013000000B4
|
||||
:10010000130000001300000013000000130E400055
|
||||
:10011000B7120000938202807390423013000000F7
|
||||
:100120001300000013000000130000001300000083
|
||||
:100130001300000013000000130E5000B70110F070
|
||||
:10014000938101F403A2010083A241001302F23F54
|
||||
:1001500023A4410023A65100130E600013020008DF
|
||||
:1001600073104230130E700073005010130E800095
|
||||
:100170009301100023A04100130E90002390410032
|
||||
:10018000130EA00003A20100130EB00003920100A1
|
||||
:10019000130EC000130ED000832000006F0020005B
|
||||
:0801A00083200000130EE000B3
|
||||
:020000044000BA
|
||||
:1000000013050000678000001305000067800000F2
|
||||
:1000100097020000678082FF1305000067800000E0
|
||||
|
@ -3192,5 +3198,5 @@
|
|||
:10C6100008C6004008C6004010C6004010C60040D2
|
||||
:10C6200018C6004018C6004080BD004080BD0040D4
|
||||
:10C6300001000000FFFFFFFF00000200C88900406A
|
||||
:040000030000007089
|
||||
:040000030000009069
|
||||
:00000001FF
|
||||
|
|
Loading…
Reference in New Issue