Hardware/VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
38 commits 39 branches 2 tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
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Charles Papon c5520656e5 Now able to catch missaligned instruction/data addresses 
Modify arbitration with an flushAll + isFlushed
2017-03-26 17:20:07 +02:00
project boot 2017-03-08 22:17:48 +01:00
src Now able to catch missaligned instruction/data addresses 2017-03-26 17:20:07 +02:00
.gitignore Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00
README.md boot 2017-03-08 22:17:48 +01:00

README.md

WIP