Fetcher/IBusSimplePlugin wip
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@ -114,10 +114,22 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public)
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val inc = RegInit(False)
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val propagatePc = False
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val pc = pcReg + (inc ## B"00").asUInt
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val samplePcNext = False
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if(compressedGen) {
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when(inc) {
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pc(1) := False
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}
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}
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when(propagatePc){
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samplePcNext := True
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inc := False
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}
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if(predictionPcLoad != null) {
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when(predictionPcLoad.valid) {
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inc := False
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@ -142,14 +154,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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pcReg := pc
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}
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if(compressedGen) {
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when(preOutput.fire) {
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pcReg(1 downto 0) := 0
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when(pc(1)){
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inc := True
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}
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}
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}
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preOutput.valid := RegNext(True) init (False)
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preOutput.payload := pc
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@ -217,7 +221,13 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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for((s,sNext) <- (stages, stages.tail).zipped) {
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sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)
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if(s == stages.head) {
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sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false))
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sNext.input.payload := fetchPc.pcReg
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fetchPc.propagatePc setWhen(sNext.input.fire)
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} else {
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sNext.input << s.output.m2sPipeWithFlush(flush, s != stages.head, collapsBubble = false)
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}
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}
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//
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@ -310,7 +320,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}).tail
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}
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val nextPcCalc = if (decodePcGen) {
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val nextPcCalc = if (decodePcGen) new Area{
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val valids = pcUpdatedGen(True, False :: List(execute, memory, writeBack).map(_.arbitration.isStuck), true)
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pcValids := Vec(valids.takeRight(4))
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} else new Area{
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@ -151,8 +151,7 @@ class IBusSimplePlugin(resetVector : BigInt,
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compressedGen : Boolean = false,
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busLatencyMin : Int = 1,
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pendingMax : Int = 7,
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injectorStage : Boolean = true,
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relaxedBusCmdValid : Boolean = false
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injectorStage : Boolean = true
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) extends IBusFetcherImpl(
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catchAccessFault = catchAccessFault,
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resetVector = resetVector,
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@ -164,8 +163,6 @@ class IBusSimplePlugin(resetVector : BigInt,
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prediction = prediction,
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historyRamSizeLog2 = historyRamSizeLog2,
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injectorStage = injectorStage){
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assert(!(prediction == DYNAMIC_TARGET && relaxedBusCmdValid), "IBusSimplePlugin doesn't allow dynamic_target prediction and relaxedBusCmdValid together")
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assert(!relaxedBusCmdValid)
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var iBus : IBusSimpleBus = null
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var decodeExceptionPort : Flow[ExceptionCause] = null
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@ -185,44 +182,23 @@ class IBusSimplePlugin(resetVector : BigInt,
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import pipeline.config._
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pipeline plug new FetchArea(pipeline) {
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//Avoid sending to many iBus cmd
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val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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val pendingCmdNext = pendingCmd + iBus.cmd.fire.asUInt - iBus.rsp.fire.asUInt
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pendingCmd := pendingCmdNext
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val cmd = if(relaxedBusCmdValid) new Area {
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???
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/* def inputStage = iBusRsp.stages(0)
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val busFork = Stream(UInt(32 bits))
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val busForkedReg = RegInit(False)
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if(!relaxedPcCalculation) busForkedReg clearWhen(flush)
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busForkedReg setWhen(iBus.cmd.fire)
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busForkedReg clearWhen(inputStage.output.ready)
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if(relaxedPcCalculation) busForkedReg clearWhen(flush)
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val busForked = Bool
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busForked := (if(!relaxedPcCalculation) (busForkedReg && !flush) else (busForkedReg))
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busFork.valid := inputStage.input.valid && !busForkedReg
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busFork.payload := inputStage.input.payload
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inputStage.halt setWhen()
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output.valid := (inputStage.input.valid && iBus.cmd.fire) || busForked
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output.payload := input.payload
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input.ready := output.fire
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val okBus = pendingCmd =/= pendingMax
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iBus.cmd.valid := busFork.valid && okBus
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iBus.cmd.pc := busFork.payload(31 downto 2) @@ "00"
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busFork.ready := iBus.cmd.ready && okBus*/
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} else new Area {
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val cmd = /*if(relaxedPcCalculation) new Area {
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//This implementation keep the iBus.cmd on the bus until it's executed, even if the pipeline is flushed
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def stage = iBusRsp.stages(1)
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stage.halt setWhen(iBus.cmd.isStall)
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val cmdKeep = RegInit(False) setWhen(iBus.cmd.valid) clearWhen(iBus.cmd.ready)
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val cmdFired = RegInit(False) setWhen(iBus.cmd.fire) clearWhen(stage.input.ready)
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iBus.cmd.valid := (stage.input.valid || cmdKeep) && pendingCmd =/= pendingMax && !cmdFired
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iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00"
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} else */new Area {
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//This implementation keep the iBus.cmd on the bus until it's executed or the the pipeline is flushed (not "safe")
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def stage = iBusRsp.stages(if(relaxedPcCalculation) 1 else 0)
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stage.halt setWhen(stage.input.valid && (!iBus.cmd.valid || !iBus.cmd.ready))
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iBus.cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax
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iBus.cmd.pc := stage.input.payload(31 downto 2) @@ "00"
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}
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@ -235,10 +211,11 @@ class IBusSimplePlugin(resetVector : BigInt,
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val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
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discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
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when(flush) {
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// discardCounter := (if(relaxedPcCalculation) pendingCmd + iBus.cmd.valid.asUInt - iBus.rsp.fire.asUInt else pendingCmd - iBus.rsp.fire.asUInt)
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discardCounter := (if(relaxedPcCalculation) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt)
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}
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val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), cmdToRspStageCount - (if(relaxedPcCalculation) 0 else 0))
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val rspBuffer = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin)
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rspBuffer.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream
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rspBuffer.io.flush := flush
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@ -249,8 +226,11 @@ class IBusSimplePlugin(resetVector : BigInt,
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var issueDetected = False
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val join = StreamJoin(Seq(stages.last.output, rspBuffer.io.pop), fetchRsp)
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stages.last.output.ready setWhen(!stages.last.output.valid)
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val join = Stream(FetchRsp())
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join.valid := stages.last.output.valid && rspBuffer.io.pop.valid
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join.payload := fetchRsp
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stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready
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rspBuffer.io.pop.ready := join.fire
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output << join.haltWhen(issueDetected)
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if(catchAccessFault){
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@ -718,11 +718,6 @@ public:
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logTraces.open (name + ".logTrace");
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fillSimELements();
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clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &start_time);
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//Sync register file initial content
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for(int i = 1;i < 32;i++){
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riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i];
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}
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}
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virtual ~Workspace(){
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@ -921,6 +916,10 @@ public:
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postReset();
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//Sync register file initial content
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for(int i = 1;i < 32;i++){
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riscvRef.regs[i] = top->VexRiscv->RegFilePlugin_regFile[i];
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}
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resetDone = true;
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#ifdef REF
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