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VexRiscv
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ClockDomainResetGeneratorIf introduction

This commit is contained in:
Dolu1990 2023-03-23 16:57:10 +01:00
parent 8195bec788
commit c69852c0cc
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -45,7 +45,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
withRiscvDebug.load(false) withRiscvDebug.load(false)
} }
def enableJtag(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ def enableJtag(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
@ -53,7 +53,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
} }
def enableJtagInstructionCtrl(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ def enableJtagInstructionCtrl(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
@ -61,7 +61,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
} }
def enableDebugBus(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator) : Unit = debugCd.rework{ def enableDebugBus(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
@ -69,7 +69,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
} }
def enableRiscvDebug(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator) : Unit = debugCd.on{ def enableRiscvDebug(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.on{
this.debugClockDomain.load(debugCd) this.debugClockDomain.load(debugCd)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withRiscvDebug.load(true) withRiscvDebug.load(true)
@ -85,7 +85,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugBmbAccessSource = Handle[BmbAccessCapabilities] val debugBmbAccessSource = Handle[BmbAccessCapabilities]
val debugBmbAccessRequirements = Handle[BmbAccessParameter] val debugBmbAccessRequirements = Handle[BmbAccessParameter]
def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{ def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{
this.debugClockDomain.load(debugCd) this.debugClockDomain.load(debugCd)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()