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VexRiscv
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Add uinstret support.

This commit is contained in:
Tom Verbeure 2020-05-19 13:40:46 -07:00
parent ddc59bc404
commit c74b03b4de
7 changed files with 25 additions and 9 deletions
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2
src/main/scala/vexriscv/Riscv.scala
View File

@ -159,5 +159,7 @@ object Riscv{
def UCYCLE = 0xC00 // UR Machine ucycle counter.
def UCYCLEH = 0xC80
def UINSTRET = 0xC02 // UR Machine instructions-retired counter.
def UINSTRETH = 0xC82 // UR Upper 32 bits of minstret, RV32I only.
}
}

3
src/main/scala/vexriscv/demo/Briey.scala
View File

@ -147,7 +147,8 @@ object BrieyConfig{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
),
new YamlPlugin("cpu0.yaml")

3
src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala
View File

@ -126,7 +126,8 @@ object VexRiscvAhbLite3{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
),
new YamlPlugin("cpu0.yaml")

3
src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
View File

@ -124,7 +124,8 @@ object VexRiscvAvalonForSim{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
),
new YamlPlugin("cpu0.yaml")

3
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
View File

@ -121,7 +121,8 @@ object VexRiscvAvalonWithIntegratedJtag{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
),
new YamlPlugin("cpu0.yaml")

3
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
View File

@ -122,7 +122,8 @@ object VexRiscvAxi4WithIntegratedJtag{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
),
new YamlPlugin("cpu0.yaml")

17
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -49,6 +49,7 @@ case class CsrPluginConfig(
mcycleAccess : CsrAccess,
minstretAccess : CsrAccess,
ucycleAccess : CsrAccess,
uinstretAccess : CsrAccess,
wfiGenAsWait : Boolean,
ecallGen : Boolean,
xtvecModeGen : Boolean = false,
@ -100,6 +101,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE,
wfiGenAsWait = true,
ecallGen = true,
xtvecModeGen = false,
@ -140,6 +142,7 @@ object CsrPluginConfig{
mcycleAccess = CsrAccess.READ_WRITE,
minstretAccess = CsrAccess.READ_WRITE,
ucycleAccess = CsrAccess.READ_ONLY,
uinstretAccess = CsrAccess.READ_ONLY,
wfiGenAsWait = true,
ecallGen = true,
xtvecModeGen = false,
@ -180,7 +183,8 @@ object CsrPluginConfig{
minstretAccess = CsrAccess.READ_WRITE,
ecallGen = true,
wfiGenAsWait = true,
ucycleAccess = CsrAccess.READ_ONLY
ucycleAccess = CsrAccess.READ_ONLY,
uinstretAccess = CsrAccess.READ_ONLY
)
def all2(mtvecInit : BigInt) : CsrPluginConfig = CsrPluginConfig(
@ -202,6 +206,7 @@ object CsrPluginConfig{
ecallGen = true,
wfiGenAsWait = true,
ucycleAccess = CsrAccess.READ_ONLY,
uinstretAccess = CsrAccess.READ_ONLY,
supervisorGen = true,
sscratchGen = true,
stvecAccess = CsrAccess.READ_WRITE,
@ -233,7 +238,8 @@ object CsrPluginConfig{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
def smallest(mtvecInit : BigInt) = CsrPluginConfig(
@ -254,7 +260,8 @@ object CsrPluginConfig{
minstretAccess = CsrAccess.NONE,
ecallGen = false,
wfiGenAsWait = false,
ucycleAccess = CsrAccess.NONE
ucycleAccess = CsrAccess.NONE,
uinstretAccess = CsrAccess.NONE
)
}
@ -586,6 +593,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
//User CSR
ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0))
ucycleAccess(CSR.UCYCLEH, mcycle(63 downto 32))
uinstretAccess(CSR.UINSTRET, minstret(31 downto 0))
uinstretAccess(CSR.UINSTRETH, minstret(63 downto 32))
pipeline(MPP) := mstatus.MPP
}
@ -1148,4 +1157,4 @@ class UserInterruptPlugin(interruptName : String, code : Int, privilege : Int =
csr.rw(csrAddress = CSR.MIE, bitOffset = code, interruptEnable)
}
override def build(pipeline: VexRiscv): Unit = {}
}
}