VexRiscvSmpClusterGen no support atomic less configs
This commit is contained in:
parent
a380c3a36c
commit
c79357d1b2
|
@ -167,6 +167,7 @@ object VexRiscvSmpClusterGen {
|
||||||
dBusWidth : Int = 64,
|
dBusWidth : Int = 64,
|
||||||
loadStoreWidth : Int = 32,
|
loadStoreWidth : Int = 32,
|
||||||
coherency : Boolean = true,
|
coherency : Boolean = true,
|
||||||
|
atomic : Boolean = true,
|
||||||
iCacheSize : Int = 8192,
|
iCacheSize : Int = 8192,
|
||||||
dCacheSize : Int = 8192,
|
dCacheSize : Int = 8192,
|
||||||
iCacheWays : Int = 2,
|
iCacheWays : Int = 2,
|
||||||
|
@ -270,9 +271,9 @@ object VexRiscvSmpClusterGen {
|
||||||
catchAccessError = true,
|
catchAccessError = true,
|
||||||
catchIllegal = true,
|
catchIllegal = true,
|
||||||
catchUnaligned = true,
|
catchUnaligned = true,
|
||||||
withLrSc = true,
|
withLrSc = atomic,
|
||||||
withAmo = true,
|
withAmo = atomic,
|
||||||
withExclusive = coherency,
|
withExclusive = atomic,
|
||||||
withInvalidate = coherency,
|
withInvalidate = coherency,
|
||||||
withWriteAggregation = dBusWidth > 32
|
withWriteAggregation = dBusWidth > 32
|
||||||
),
|
),
|
||||||
|
|
Loading…
Reference in New Issue