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VexRiscv
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Merge branch 'spinal_1.4.4' into dev

This commit is contained in:
Dolu1990 2021-07-05 11:37:53 +02:00
parent 3702ea03c0 551e76d244
commit a380c3a36c
1 changed files with 26 additions and 1 deletions
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27
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -193,6 +193,31 @@ object VexRiscvSmpClusterGen {
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
assert(!(withDouble && !withFloat))
val csrConfig = if(withSupervisor){
CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)
} else {
CsrPluginConfig(
catchIllegalAccess = true,
mvendorid = null,
marchid = null,
mimpid = null,
mhartid = 0,
misaExtensionsInit = 0,
misaAccess = CsrAccess.NONE,
mtvecAccess = CsrAccess.READ_WRITE,
mtvecInit = null,
mepcAccess = CsrAccess.READ_WRITE,
mscratchGen = false,
mcauseAccess = CsrAccess.READ_ONLY,
mbadaddrAccess = CsrAccess.READ_ONLY,
mcycleAccess = CsrAccess.NONE,
minstretAccess = CsrAccess.NONE,
ecallGen = true,
wfiGenAsWait = false,
wfiGenAsNop = true,
ucycleAccess = CsrAccess.NONE
)
}
val config = VexRiscvConfig(
plugins = List(
if(withMmu)new MmuPlugin(
@ -290,7 +315,7 @@ object VexRiscvSmpClusterGen {
mulUnrollFactor = 32,
divUnrollFactor = 1
),
new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)),
new CsrPlugin(csrConfig),
new BranchPlugin(
earlyBranch = earlyBranch,
catchAddressMisaligned = true,