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MulPlugin now add KEEP attribute on RS1 and RS2 to force Vivado to not retime it with the DSP

This commit is contained in:
Charles Papon 2020-02-23 20:25:31 +01:00
parent 01e5112680
commit c8016e90a4
1 changed files with 7 additions and 0 deletions
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7
src/main/scala/vexriscv/plugin/MulPlugin.scala
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@ -2,6 +2,7 @@ package vexriscv.plugin
import vexriscv._ import vexriscv._
import vexriscv.VexRiscv import vexriscv.VexRiscv
import spinal.core._ import spinal.core._
import spinal.lib.KeepAttribute
//Input buffer generaly avoid the FPGA synthesis to duplicate reg inside the DSP cell, which could stress timings quite much. //Input buffer generaly avoid the FPGA synthesis to duplicate reg inside the DSP cell, which could stress timings quite much.
class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{ class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{
@ -94,6 +95,12 @@ class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{
insert(MUL_LH) := aSLow * bHigh insert(MUL_LH) := aSLow * bHigh
insert(MUL_HL) := aHigh * bSLow insert(MUL_HL) := aHigh * bSLow
insert(MUL_HH) := aHigh * bHigh insert(MUL_HH) := aHigh * bHigh
Component.current.afterElaboration{
//Avoid synthesis tools to retime RS1 RS2 from execute stage to decode stage leading to bad timings (ex : Vivado, even if retiming is disabled)
KeepAttribute(input(RS1).getDrivingReg)
KeepAttribute(input(RS2).getDrivingReg)
}
} }
//First aggregation of partial multiplication //First aggregation of partial multiplication