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Update IBusCachedPlugin parameters

This commit is contained in:
Dolu1990 2018-05-16 12:11:53 +02:00
parent 3b54ecf303
commit c8cec59f1d
4 changed files with 21 additions and 13 deletions
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1
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -40,6 +40,7 @@ object TestsWorkspace {
// compressedGen = true // compressedGen = true
// ), // ),
new IBusCachedPlugin( new IBusCachedPlugin(
resetVector = 0x80000000l,
config = InstructionCacheConfig( config = InstructionCacheConfig(
cacheSize = 1024*16, cacheSize = 1024*16,
bytePerLine = 32, bytePerLine = 32,

2
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -17,7 +17,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val injectorReadyCutGen : Boolean, val injectorReadyCutGen : Boolean,
val relaxedPcCalculation : Boolean, val relaxedPcCalculation : Boolean,
val prediction : BranchPrediction, val prediction : BranchPrediction,
val catchAddressMisaligned : Boolean, val catchAddressMisaligned : Boolean, //Catch broken prediction ?
val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ val injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
var prefetchExceptionPort : Flow[ExceptionCause] = null var prefetchExceptionPort : Flow[ExceptionCause] = null

23
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
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@ -9,17 +9,24 @@ import spinal.lib._
// var iBus : InstructionCacheMemBus = null // var iBus : InstructionCacheMemBus = null
// override def build(pipeline: VexRiscv): Unit = ??? // override def build(pipeline: VexRiscv): Unit = ???
//} //}
class IBusCachedPlugin(config : InstructionCacheConfig, memoryTranslatorPortConfig : Any = null) extends IBusFetcherImpl( class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
relaxedPcCalculation : Boolean = false,
prediction : BranchPrediction = NONE,
compressedGen : Boolean = false,
keepPcPlus4 : Boolean = false,
catchAddressMisaligned : Boolean = false,
config : InstructionCacheConfig,
memoryTranslatorPortConfig : Any = null) extends IBusFetcherImpl(
catchAccessFault = config.catchAccessFault, catchAccessFault = config.catchAccessFault,
resetVector = BigInt(0x80000000l), resetVector = resetVector,
keepPcPlus4 = false, keepPcPlus4 = keepPcPlus4,
decodePcGen = true, decodePcGen = compressedGen,
compressedGen = true, compressedGen = compressedGen,
cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1), cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1),
injectorReadyCutGen = false, injectorReadyCutGen = false,
relaxedPcCalculation = false, relaxedPcCalculation = relaxedPcCalculation,
prediction = NONE, prediction = prediction,
catchAddressMisaligned = false, catchAddressMisaligned = catchAddressMisaligned,
injectorStage = !config.twoCycleCache){ injectorStage = !config.twoCycleCache){
import config._ import config._

8
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
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@ -104,10 +104,10 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
class IBusSimplePlugin(resetVector : BigInt, class IBusSimplePlugin(resetVector : BigInt,
relaxedPcCalculation : Boolean, catchAccessFault : Boolean = false,
prediction : BranchPrediction, catchAddressMisaligned : Boolean = false,
catchAccessFault : Boolean, relaxedPcCalculation : Boolean = false,
catchAddressMisaligned : Boolean, prediction : BranchPrediction = NONE,
keepPcPlus4 : Boolean = false, keepPcPlus4 : Boolean = false,
compressedGen : Boolean = false, compressedGen : Boolean = false,
busLatencyMin : Int = 1, busLatencyMin : Int = 1,