revert removed code by mistake
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@ -8,7 +8,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
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* Created by spinalvm on 15.06.17.
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*/
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//make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no
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//make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no CUSTOM_CSR=yes
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object GenCustomCsr extends App{
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def cpu() = new VexRiscv(
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config = VexRiscvConfig(
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@ -129,11 +129,6 @@ case class CsrMapping() extends CsrInterface{
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}
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trait IContextSwitching{
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def isContextSwitching : Bool
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}
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trait CsrInterface{
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def r(csrAddress : Int, bitOffset : Int, that : Data): Unit
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def w(csrAddress : Int, bitOffset : Int, that : Data): Unit
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@ -149,6 +144,10 @@ trait CsrInterface{
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}
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trait IContextSwitching{
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def isContextSwitching : Bool
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}
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class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
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import config._
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import CsrAccess._
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@ -463,9 +462,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
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execute plug new Area {
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import execute._
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val illegalAccess = True
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val illegalAccess = arbitration.isValid && input(IS_CSR)
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if(catchIllegalAccess) {
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selfException.valid := arbitration.isValid && input(IS_CSR) && illegalAccess
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val illegalInstruction = arbitration.isValid && privilege === 0 && (input(ENV_CTRL) === EnvCtrlEnum.EBREAK || input(ENV_CTRL) === EnvCtrlEnum.MRET)
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selfException.valid := illegalAccess || illegalInstruction
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selfException.code := 2
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selfException.badAddr.assignDontCare()
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}
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