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VexRiscv
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revert removed code by mistake

This commit is contained in:
Dolu1990 2018-01-31 18:29:30 +01:00
parent 30b05eaf96
commit d2e5755df4
2 changed files with 9 additions and 8 deletions
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2
src/main/scala/vexriscv/demo/GenCustomCsr.scala
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@ -8,7 +8,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
* Created by spinalvm on 15.06.17. * Created by spinalvm on 15.06.17.
*/ */
//make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no //make clean run DBUS=SIMPLE IBUS=SIMPLE CSR=no MMU=no DEBUG_PLUGIN=no MUL=no DIV=no CUSTOM_CSR=yes
object GenCustomCsr extends App{ object GenCustomCsr extends App{
def cpu() = new VexRiscv( def cpu() = new VexRiscv(
config = VexRiscvConfig( config = VexRiscvConfig(

15
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -129,11 +129,6 @@ case class CsrMapping() extends CsrInterface{
} }
trait IContextSwitching{
def isContextSwitching : Bool
}
trait CsrInterface{ trait CsrInterface{
def r(csrAddress : Int, bitOffset : Int, that : Data): Unit def r(csrAddress : Int, bitOffset : Int, that : Data): Unit
def w(csrAddress : Int, bitOffset : Int, that : Data): Unit def w(csrAddress : Int, bitOffset : Int, that : Data): Unit
@ -149,6 +144,10 @@ trait CsrInterface{
} }
trait IContextSwitching{
def isContextSwitching : Bool
}
class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
import config._ import config._
import CsrAccess._ import CsrAccess._
@ -463,9 +462,11 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
execute plug new Area { execute plug new Area {
import execute._ import execute._
val illegalAccess = True val illegalAccess = arbitration.isValid && input(IS_CSR)
if(catchIllegalAccess) { if(catchIllegalAccess) {
selfException.valid := arbitration.isValid && input(IS_CSR) && illegalAccess val illegalInstruction = arbitration.isValid && privilege === 0 && (input(ENV_CTRL) === EnvCtrlEnum.EBREAK || input(ENV_CTRL) === EnvCtrlEnum.MRET)
selfException.valid := illegalAccess || illegalInstruction
selfException.code := 2 selfException.code := 2
selfException.badAddr.assignDontCare() selfException.badAddr.assignDontCare()
} }