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smp cluster now have 2w*4KB of d$ , no more rdtime emulation

This commit is contained in:
Dolu1990 2020-06-05 10:43:00 +02:00
parent 71760ea372
commit d6455817e7
1 changed files with 4 additions and 4 deletions
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8
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -9,7 +9,7 @@ import spinal.lib.bus.bmb.{Bmb, BmbArbiter, BmbDecoder, BmbExclusiveMonitor, Bmb
import spinal.lib.com.jtag.Jtag import spinal.lib.com.jtag.Jtag
import spinal.lib.com.jtag.sim.JtagTcp import spinal.lib.com.jtag.sim.JtagTcp
import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig} import vexriscv.ip.{DataCacheAck, DataCacheConfig, DataCacheMemBus, InstructionCache, InstructionCacheConfig}
import vexriscv.plugin.{BranchPlugin, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin} import vexriscv.plugin.{BranchPlugin, CsrAccess, CsrPlugin, CsrPluginConfig, DBusCachedPlugin, DBusSimplePlugin, DYNAMIC_TARGET, DebugPlugin, DecoderSimplePlugin, FullBarrelShifterPlugin, HazardSimplePlugin, IBusCachedPlugin, IBusSimplePlugin, IntAluPlugin, MmuPlugin, MmuPortConfig, MulDivIterativePlugin, MulPlugin, RegFilePlugin, STATIC, SrcPlugin, YamlPlugin}
import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin} import vexriscv.{Riscv, VexRiscv, VexRiscvConfig, plugin}
import scala.collection.mutable import scala.collection.mutable
@ -160,9 +160,9 @@ object VexRiscvSmpClusterGen {
dBusRspSlavePipe = true, dBusRspSlavePipe = true,
relaxedMemoryTranslationRegister = true, relaxedMemoryTranslationRegister = true,
config = new DataCacheConfig( config = new DataCacheConfig(
cacheSize = 4096*1, cacheSize = 4096*2,
bytePerLine = 64, bytePerLine = 64,
wayCount = 1, wayCount = 2,
addressWidth = 32, addressWidth = 32,
cpuDataWidth = 32, cpuDataWidth = 32,
memDataWidth = dBusWidth, memDataWidth = dBusWidth,
@ -213,7 +213,7 @@ object VexRiscvSmpClusterGen {
mulUnrollFactor = 32, mulUnrollFactor = 32,
divUnrollFactor = 1 divUnrollFactor = 1
), ),
new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas"))), new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)),
new BranchPlugin( new BranchPlugin(
earlyBranch = false, earlyBranch = false,
catchAddressMisaligned = true, catchAddressMisaligned = true,