Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

usetRegIfNoAssign upgrade

This commit is contained in:
Dolu1990 2017-11-09 20:10:56 +01:00
parent ba42f71813
commit d6777ae8ec
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View File

@ -337,7 +337,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{ val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min
val exceptionValids = Vec(Bool,stages.length) val exceptionValids = Vec(Bool,stages.length)
val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length) val exceptionValidsRegs = Vec(Reg(Bool) init(False), stages.length).unsetRegIfNoAssignement
val exceptionContext = Reg(ExceptionCause()) val exceptionContext = Reg(ExceptionCause())
val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined val pipelineHasException = exceptionValids.orR //TODO FMAX maybe could be partialy pipelined