Fix ICache exception priority over miss reload

This commit is contained in:
Dolu1990 2018-02-19 22:44:46 +01:00
parent 0270ee26fa
commit d957934949
2 changed files with 11 additions and 11 deletions

View File

@ -77,15 +77,15 @@ case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle
val isUser = Bool val isUser = Bool
val isStuck = Bool val isStuck = Bool
val pc = UInt(p.addressWidth bits) val pc = UInt(p.addressWidth bits)
val redo = Bool val cacheMiss = Bool
val data = ifGen(p.dataOnDecode) (Bits(p.cpuDataWidth bits)) val data = ifGen(p.dataOnDecode) (Bits(p.cpuDataWidth bits))
val error = if(p.catchAccessFault) Bool else null val error = Bool
val mmuMiss = if(p.catchMemoryTranslationMiss) Bool else null val mmuMiss = Bool
val illegalAccess = if(p.catchIllegalAccess) Bool else null val illegalAccess =Bool
override def asMaster(): Unit = { override def asMaster(): Unit = {
out(isValid, isUser, isStuck, pc) out(isValid, isUser, isStuck, pc)
in(redo) in(cacheMiss)
inWithNull(error,mmuMiss,illegalAccess,data) inWithNull(error,mmuMiss,illegalAccess,data)
} }
} }
@ -334,16 +334,16 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
} }
} }
io.cpu.decode.redo := io.cpu.decode.isValid && !hit.valid io.cpu.decode.cacheMiss := !hit.valid
when(io.cpu.decode.redo){ when( io.cpu.decode.isValid && io.cpu.decode.cacheMiss){
io.cpu.prefetch.haltIt := True io.cpu.prefetch.haltIt := True
lineLoader.valid := True lineLoader.valid := True
lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used lineLoader.address := mmuRsp.physicalAddress //Could be optimise if mmu not used
} }
if(catchAccessFault) io.cpu.decode.error := hit.error io.cpu.decode.error := hit.error
if(catchMemoryTranslationMiss) io.cpu.decode.mmuMiss := mmuRsp.miss io.cpu.decode.mmuMiss := mmuRsp.miss
if(catchIllegalAccess) io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser) io.cpu.decode.illegalAccess := !mmuRsp.allowExecute || (io.cpu.decode.isUser && !mmuRsp.allowUser)
} }
} }

View File

@ -112,7 +112,7 @@ class IBusCachedPlugin(config : InstructionCacheConfig, askMemoryTranslation : B
cache.io.cpu.decode.isUser := (if(privilegeService != null) privilegeService.isUser(decode) else False) cache.io.cpu.decode.isUser := (if(privilegeService != null) privilegeService.isUser(decode) else False)
// cache.io.cpu.decode.pc := decode.input(PC) // cache.io.cpu.decode.pc := decode.input(PC)
redoBranch.valid := cache.io.cpu.decode.redo redoBranch.valid := decode.arbitration.isValid && ownDecode && cache.io.cpu.decode.cacheMiss && !cache.io.cpu.decode.mmuMiss && !cache.io.cpu.decode.illegalAccess
redoBranch.payload := decode.input(PC) redoBranch.payload := decode.input(PC)
when(redoBranch.valid){ when(redoBranch.valid){
decode.arbitration.redoIt := True decode.arbitration.redoIt := True