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VexRiscv
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Do not allow jtag ebreak outside machine mode

This commit is contained in:
Dolu1990 2020-10-28 12:58:24 +01:00
parent 4209dc2792
commit dc9246715d
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -195,8 +195,9 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
}
}
val allowEBreak = if(!pipeline.serviceExist(classOf[PrivilegeService])) True else pipeline.service(classOf[PrivilegeService]).isMachine()
decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _))
decode.insert(DO_EBREAK) := !haltIt && (decode.input(IS_EBREAK) || hardwareBreakpoints.map(hb => hb.valid && hb.pc === (decode.input(PC) >> 1)).foldLeft(False)(_ || _)) && allowEBreak
when(execute.arbitration.isValid && execute.input(DO_EBREAK)){
execute.arbitration.haltByOther := True
busReadDataReg := execute.input(PC).asBits