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VexRiscv
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fix run-main into runMain

This commit is contained in:
Dolu1990 2019-01-03 20:07:38 +01:00
parent 414d2aba54
commit dcdfa79024
4 changed files with 13 additions and 13 deletions
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14
README.md
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@ -162,13 +162,13 @@ You can find two example CPU instances in:
To generate the corresponding RTL as a VexRiscv.v file, run the following commands in the root directory of this repository:
```sh
sbt "run-main vexriscv.demo.GenFull"
sbt "runMain vexriscv.demo.GenFull"
```
or
```sh
sbt "run-main vexriscv.demo.GenSmallest"
sbt "runMain vexriscv.demo.GenSmallest"
```
NOTES:
@ -204,7 +204,7 @@ Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a
```sh
#in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself =>
sbt "run-main vexriscv.demo.GenFull"
sbt "runMain vexriscv.demo.GenFull"
cd src/test/cpp/regression
make run DEBUG_PLUGIN_EXTERNAL=yes
@ -254,7 +254,7 @@ the [Pinsec SOC](https://spinalhdl.github.io/SpinalDoc/spinal/lib/pinsec/hardwar
To generate the Briey SoC Hardware:
```sh
sbt "run-main vexriscv.demo.Briey"
sbt "runMain vexriscv.demo.Briey"
```
To run the verilator simulation of the Briey SoC which can then be connected to OpenOCD/GDB, first get those dependencies:
@ -309,10 +309,10 @@ To generate the Murax SoC Hardware :
```sh
# To generate the SoC without any content in the ram
sbt "run-main vexriscv.demo.Murax"
sbt "runMain vexriscv.demo.Murax"
# To generate the SoC with a demo program already in ram
sbt "run-main vexriscv.demo.MuraxWithRamInit"
sbt "runMain vexriscv.demo.MuraxWithRamInit"
```
The demo program included by default with `MuraxWithRamInit` will blink the
@ -560,7 +560,7 @@ and is self-tested by the `src/test/cpp/custom/simd_add` application by running
```sh
# Generate the CPU
sbt "run-main vexriscv.demo.GenCustomSimdAdd"
sbt "runMain vexriscv.demo.GenCustomSimdAdd"
cd src/test/cpp/regression/

4
scripts/Murax/iCE40-hx8k_breakout_board/Makefile
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@ -3,10 +3,10 @@
VERILOG = ../../../Murax.v toplevel.v
generate :
(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
../../../Murax.v :
(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
../../../Murax.v*.bin:

4
scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile
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@ -3,10 +3,10 @@
VERILOG = ../../../Murax_iCE40_hx8k_breakout_board_xip.v
generate :
#(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
#(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
../../../Murax_iCE40_hx8k_breakout_board_xip.v :
#(cd ../../..; sbt "run-main vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
#(cd ../../..; sbt "runMain vexriscv.demo.Murax_iCE40_hx8k_breakout_board_xip")
../../../Murax_iCE40_hx8k_breakout_board_xip.v*.bin:

4
scripts/Murax/iCE40HX8K-EVB/Makefile
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@ -3,10 +3,10 @@
VERILOG = ../../../Murax.v toplevel.v toplevel_pll.v
generate :
(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
../../../Murax.v :
(cd ../../..; sbt "run-main vexriscv.demo.MuraxWithRamInit")
(cd ../../..; sbt "runMain vexriscv.demo.MuraxWithRamInit")
../../../Murax.v*.bin: