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VexRiscv
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Merge remote-tracking branch 'origin/master' into dev

This commit is contained in:
Dolu1990 2018-12-29 14:04:07 +01:00
parent 76ebfb2243 1da055dc34
commit dd42e30c61
3 changed files with 4 additions and 4 deletions
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4
README.md
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@ -26,7 +26,7 @@
This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs : This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs :
- RV32I[M] instruction set - RV32I[M][C] instruction set
- Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack) - Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
- 1.44 DMIPS/Mhz --no-inline when nearly all features are enabled (1.57 DMIPS/Mhz when the divider lookup table is enabled) - 1.44 DMIPS/Mhz --no-inline when nearly all features are enabled (1.57 DMIPS/Mhz when the divider lookup table is enabled)
- Optimized for FPGA, fully portable - Optimized for FPGA, fully portable
@ -159,7 +159,7 @@ You can find two example CPU instances in:
- src/main/scala/vexriscv/GenFull.scala - src/main/scala/vexriscv/GenFull.scala
- src/main/scala/vexriscv/GenSmallest.scala - src/main/scala/vexriscv/GenSmallest.scala
To generate the corresponding RTL as a VexRiscv.v file, run: To generate the corresponding RTL as a VexRiscv.v file, run the following commands in the root directory of this repository:
```sh ```sh
sbt "run-main vexriscv.demo.GenFull" sbt "run-main vexriscv.demo.GenFull"

2
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
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@ -162,7 +162,7 @@ object VexRiscvAvalonWithIntegratedJtag{
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess() plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag()) val jtag = slave(new Jtag())
.setName("jtag") .setName("jtag")

2
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
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@ -163,7 +163,7 @@ object VexRiscvAxi4WithIntegratedJtag{
.setName("dBusAxi") .setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => plugin.debugClockDomain {
plugin.io.bus.setAsDirectionLess() plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag()) val jtag = slave(new Jtag())
.setName("jtag") .setName("jtag")