Merge remote-tracking branch 'origin/master' into dev

README.md

@@ -26,7 +26,7 @@
 
 This repository hosts a RISC-V implementation written in SpinalHDL. Here are some specs :
 
-- RV32I[M] instruction set
+- RV32I[M][C] instruction set
 - Pipelined with 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
 - 1.44 DMIPS/Mhz --no-inline when nearly all features are enabled (1.57 DMIPS/Mhz when the divider lookup table is enabled)
 - Optimized for FPGA, fully portable
@@ -159,7 +159,7 @@ You can find two example CPU instances in:
 - src/main/scala/vexriscv/GenFull.scala
 - src/main/scala/vexriscv/GenSmallest.scala
 
-To generate the corresponding RTL as a VexRiscv.v file, run:
+To generate the corresponding RTL as a VexRiscv.v file, run the following commands in the root directory of this repository:
 
 ```sh
 sbt "run-main vexriscv.demo.GenFull"

src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala

@@ -162,7 +162,7 @@ object VexRiscvAvalonWithIntegratedJtag{
               .setName("dBusAvalon")
               .addTag(ClockDomainTag(ClockDomain.current))
           }
-          case plugin: DebugPlugin => {
+          case plugin: DebugPlugin => plugin.debugClockDomain {
             plugin.io.bus.setAsDirectionLess()
             val jtag = slave(new Jtag())
               .setName("jtag")

src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala

@@ -163,7 +163,7 @@ object VexRiscvAxi4WithIntegratedJtag{
               .setName("dBusAxi")
               .addTag(ClockDomainTag(ClockDomain.current))
           }
-          case plugin: DebugPlugin => {
+          case plugin: DebugPlugin => plugin.debugClockDomain {
             plugin.io.bus.setAsDirectionLess()
             val jtag = slave(new Jtag())
               .setName("jtag")