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add earlyBranch option to Smp config

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This commit is contained in:
Dolu1990 2020-09-13 18:33:06 +02:00
parent 49488d19af
commit de820daf74
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -158,7 +158,8 @@ object VexRiscvSmpClusterGen {
dCacheSize : Int = 8192, dCacheSize : Int = 8192,
iCacheWays : Int = 2, iCacheWays : Int = 2,
dCacheWays : Int = 2, dCacheWays : Int = 2,
iBusRelax : Boolean = false) = { iBusRelax : Boolean = false,
earlyBranch : Boolean = true) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes") assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes") assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
val config = VexRiscvConfig( val config = VexRiscvConfig(
@ -257,7 +258,7 @@ object VexRiscvSmpClusterGen {
), ),
new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)), new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt("imas")).copy(utimeAccess = CsrAccess.READ_ONLY)),
new BranchPlugin( new BranchPlugin(
earlyBranch = true, earlyBranch = earlyBranch,
catchAddressMisaligned = true, catchAddressMisaligned = true,
fenceiGenAsAJump = false fenceiGenAsAJump = false
), ),