wip
This commit is contained in:
Dolu1990
parent
d9f2e03753
commit
e00c0750eb
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@ -122,7 +122,7 @@ object TestsWorkspace {
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),
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// new DivPlugin,
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new CsrPlugin(CsrPluginConfig.all(0x80000020l).copy(deterministicInteruptionEntry = false)),
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new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
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new BranchPlugin(
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earlyBranch = true,
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catchAddressMisaligned = true,
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@ -81,7 +81,7 @@ case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle
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val data = ifGen(p.dataOnDecode) (Bits(p.cpuDataWidth bits))
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val error = Bool
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val mmuMiss = Bool
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val illegalAccess =Bool
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val illegalAccess = Bool
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override def asMaster(): Unit = {
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out(isValid, isUser, isStuck, pc)
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@ -0,0 +1,327 @@
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package vexriscv.plugin
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import vexriscv._
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import spinal.core._
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import spinal.lib._
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import vexriscv.Riscv.IMM
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import StreamVexPimper._
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import scala.collection.mutable.ArrayBuffer
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abstract class IBusFetcherImpl(catchAccessFault : Boolean,
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pendingMax : Int = 7,
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resetVector : BigInt,
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keepPcPlus4 : Boolean,
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decodePcGen : Boolean,
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compressedGen : Boolean,
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cmdToRspStageCount : Int,
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rspStageGen : Boolean,
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injectorReadyCutGen : Boolean,
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relaxedPcCalculation : Boolean,
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prediction : BranchPrediction,
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catchAddressMisaligned : Boolean,
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injectorStage : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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var decodePrediction : DecodePredictionBus = null
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assert(cmdToRspStageCount >= 1)
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assert(!(compressedGen && !decodePcGen))
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var fetcherHalt : Bool = null
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lazy val decodeNextPcValid = Bool
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lazy val decodeNextPc = UInt(32 bits)
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def nextPc() = (decodeNextPcValid, decodeNextPc)
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = {
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val interface = Flow(UInt(32 bits))
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jumpInfos += JumpInfo(interface,stage, priority)
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interface
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}
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var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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fetcherHalt = False
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if(catchAccessFault || catchAddressMisaligned) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1).setName("iBusErrorExceptionnPort")
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}
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pipeline(RVC_GEN) = compressedGen
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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}
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}
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class FetchArea(pipeline : VexRiscv) extends Area {
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import pipeline._
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import pipeline.config._
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//JumpService hardware implementation
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val jump = new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => {
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(pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) ||
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(pipeline.indexOf(a.stage) == pipeline.indexOf(b.stage) && a.priority > b.priority)
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})
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val valids = sortedByStage.map(_.interface.valid)
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val pcs = sortedByStage.map(_.interface.payload)
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val pcLoad = Flow(UInt(32 bits))
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pcLoad.valid := jumpInfos.map(_.interface.valid).orR
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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}
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val killLastStage = jump.pcLoad.valid || decode.arbitration.isRemoved
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def flush = killLastStage
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class PcFetch extends Area{
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val output = Stream(UInt(32 bits))
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}
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val fetchPc = if(relaxedPcCalculation) new PcFetch {
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
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val pcPlus4 = pcReg + 4
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if (keepPcPlus4) KeepAttribute(pcPlus4)
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when(output.fire) {
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pcReg := pcPlus4
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}
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//Realign
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if(compressedGen){
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when(output.fire){
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pcReg(1 downto 0) := 0
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}
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}
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//application of the selected jump request
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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output.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
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output.payload := pcReg
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} else new PcFetch{
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
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val inc = RegInit(False)
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val pc = pcReg + (inc ## B"00").asUInt
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val samplePcNext = False
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when(jump.pcLoad.valid) {
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inc := False
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samplePcNext := True
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pc := jump.pcLoad.payload
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}
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when(output.fire){
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inc := True
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samplePcNext := True
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}
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when(samplePcNext) {
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pcReg := pc
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}
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if(compressedGen) {
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when(output.fire) {
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pcReg(1 downto 0) := 0
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when(pc(1)){
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inc := True
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}
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}
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}
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output.valid := RegNext(True) init (False)
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output.payload := pc
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}
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val decodePc = ifGen(decodePcGen)(new Area {
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//PC calculation without Jump
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val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
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val pcPlus = if(compressedGen)
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pcReg + ((decode.input(IS_RVC)) ? U(2) | U(4))
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else
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pcReg + 4
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if (keepPcPlus4) KeepAttribute(pcPlus)
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when(decode.arbitration.isFiring) {
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pcReg := pcPlus
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}
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//application of the selected jump request
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when(jump.pcLoad.valid) {
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pcReg := jump.pcLoad.payload
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}
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})
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val iBusCmd = new Area {
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def input = fetchPc.output
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// ...
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val output = Stream(UInt(32 bits))
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}
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case class FetchRsp() extends Bundle {
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val pc = UInt(32 bits)
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val rsp = IBusSimpleRsp()
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val isRvc = Bool
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}
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val iBusRsp = new Area {
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val inputStages = Vec(Stream(UInt(32 bits)), cmdToRspStageCount)
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for(i <- 0 until cmdToRspStageCount) {
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// val doFlush = if(i == cmdToRspStageCount- 1 && ???) killLastStage else flush
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inputStages(i) << {i match {
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case 0 => iBusCmd.output.m2sPipeWithFlush(flush, relaxedPcCalculation)
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case _ => inputStages(i-1)/*.haltWhen(fetcherHalt)*/.m2sPipeWithFlush(flush)
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}}
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}
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def input = inputStages.last
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// ...
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val join = Stream(FetchRsp())
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val output = if(rspStageGen) join.m2sPipeWithFlush(flush) else join
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}
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val decompressor = ifGen(decodePcGen)(new Area{
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def input = iBusRsp.output
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val output = Stream(FetchRsp())
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val bufferValid = RegInit(False)
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val bufferError = Reg(Bool)
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val bufferData = Reg(Bits(16 bits))
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val raw = Mux(
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sel = bufferValid,
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whenTrue = input.rsp.inst(15 downto 0) ## bufferData,
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whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
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)
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val isRvc = raw(1 downto 0) =/= 3
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val decompressed = RvcDecompressor(raw(15 downto 0))
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output.valid := isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))
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output.pc := input.pc
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output.isRvc := isRvc
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output.rsp.inst := isRvc ? decompressed | raw
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output.rsp.error := (bufferValid && bufferError) || (input.valid && input.rsp.error && (!isRvc || (isRvc && !bufferValid)))
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input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
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bufferValid clearWhen(output.fire)
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when(input.ready){
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when(input.valid) {
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bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1))
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bufferError := input.rsp.error
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bufferData := input.rsp.inst(31 downto 16)
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}
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}
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bufferValid.clearWhen(flush)
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})
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def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
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val injector = new Area {
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val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
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val decodeInput = if(injectorStage){
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val inputBeforeStage = inputBeforeHalt.haltWhen(fetcherHalt)
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val decodeInput = inputBeforeStage.m2sPipeWithFlush(killLastStage)
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decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst)
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decodeInput
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} else {
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inputBeforeHalt
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}
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if(decodePcGen){
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decodeNextPcValid := True
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decodeNextPc := decodePc.pcReg
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}else {
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val lastStageStream = if(injectorStage) inputBeforeHalt
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else if(rspStageGen) iBusRsp.join
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else if(cmdToRspStageCount > 1)iBusRsp.inputStages(cmdToRspStageCount-2)
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else throw new Exception("Fetch should at least have two stages")
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// when(fetcherHalt){
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// lastStageStream.valid := False
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// lastStageStream.ready := False
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// }
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decodeNextPcValid := RegNext(lastStageStream.isStall)
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decodeNextPc := decode.input(PC)
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}
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decodeInput.ready := !decode.arbitration.isStuck
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decode.arbitration.isValid := decodeInput.valid
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decode.insert(PC) := (if(decodePcGen) decodePc.pcReg else decodeInput.pc)
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decode.insert(INSTRUCTION) := decodeInput.rsp.inst
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decode.insert(INSTRUCTION_READY) := True
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if(compressedGen) decode.insert(IS_RVC) := decodeInput.isRvc
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if(catchAccessFault){
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decodeExceptionPort.valid := decode.arbitration.isValid && decodeInput.rsp.error
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decodeExceptionPort.code := 1
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decodeExceptionPort.badAddr := decode.input(PC)
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}
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}
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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def historyWidth = 2
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def historyRamSizeLog2 = 10
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// if(prediction == DYNAMIC) {
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// case class BranchPredictorLine() extends Bundle{
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// val history = SInt(historyWidth bits)
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// }
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//
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// val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
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// val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
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//
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//
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// val readAddress = (2, historyRamSizeLog2 bits)
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// fetch.insert(HISTORY_LINE) := historyCache.readSync(readAddress,!prefetch.arbitration.isStuckByOthers)
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//
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// }
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val imm = IMM(decode.input(INSTRUCTION))
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val conditionalBranchPrediction = (prediction match {
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case STATIC => imm.b_sext.msb
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// case DYNAMIC => decodeHistory.history.msb
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})
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decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
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predictionJumpInterface.valid := decodePrediction.cmd.hadBranch && decode.arbitration.isFiring //TODO OH Doublon de priorité
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predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
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if(catchAddressMisaligned) {
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???
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// predictionExceptionPort.valid := input(INSTRUCTION_READY) && input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
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// predictionExceptionPort.code := 0
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// predictionExceptionPort.badAddr := predictionJumpInterface.payload
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}
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}
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}
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}
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}
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@ -5,9 +5,7 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi._
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import vexriscv.Riscv.IMM
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import scala.collection.mutable.ArrayBuffer
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case class IBusSimpleCmd() extends Bundle{
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@ -105,171 +103,50 @@ case class IBusSimpleBus(interfaceKeepData : Boolean) extends Bundle with IMaste
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class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean, pendingMax : Int = 7) extends Plugin[VexRiscv] with JumpService with IBusFetcher{
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class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean, pendingMax : Int = 7) extends IBusFetcherImpl(
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catchAccessFault = catchAccessFault,
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pendingMax = 7,
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resetVector = BigInt(0x80000000l),
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keepPcPlus4 = false,
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decodePcGen = false,
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compressedGen = false,
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cmdToRspStageCount = 1,
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rspStageGen = false,
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injectorReadyCutGen = false,
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relaxedPcCalculation = false,
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prediction = NONE,
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catchAddressMisaligned = false,
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injectorStage = true){
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var iBus : IBusSimpleBus = null
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var prefetchExceptionPort : Flow[ExceptionCause] = null
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def resetVector = BigInt(0x80000000l)
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def keepPcPlus4 = false
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def decodePcGen = true
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def compressedGen = true
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def decodePcGen = false
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def compressedGen = false
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def cmdToRspStageCount = 1
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def rspStageGen = false
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def injectorReadyCutGen = false
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def relaxedPcCalculation = false
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def prediction : BranchPrediction = STATIC
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def catchAddressMisaligned = true
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var decodePrediction : DecodePredictionBus = null
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assert(cmdToRspStageCount >= 1)
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assert(!(compressedGen && !decodePcGen))
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lazy val fetcherHalt = False
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lazy val decodeNextPcValid = Bool
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lazy val decodeNextPc = UInt(32 bits)
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def nextPc() = (decodeNextPcValid, decodeNextPc)
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var predictionJumpInterface : Flow[UInt] = null
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override def haltIt(): Unit = fetcherHalt := True
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case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int)
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val jumpInfos = ArrayBuffer[JumpInfo]()
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override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = {
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val interface = Flow(UInt(32 bits))
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jumpInfos += JumpInfo(interface,stage, priority)
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interface
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}
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def prediction : BranchPrediction = NONE
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def catchAddressMisaligned = false
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def injectorStage = true
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var decodeExceptionPort : Flow[ExceptionCause] = null
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override def setup(pipeline: VexRiscv): Unit = {
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super.setup(pipeline)
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iBus = master(IBusSimpleBus(interfaceKeepData)).setName("iBus")
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if(catchAccessFault) {
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val exceptionService = pipeline.service(classOf[ExceptionService])
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decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1).setName("iBusErrorExceptionnPort")
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}
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pipeline(RVC_GEN) = compressedGen
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prediction match {
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case NONE =>
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case STATIC | DYNAMIC => {
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predictionJumpInterface = createJumpInterface(pipeline.decode)
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decodePrediction = pipeline.service(classOf[PredictionInterface]).askDecodePrediction()
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}
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}
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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pipeline plug new Area {
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pipeline plug new FetchArea(pipeline) {
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//JumpService hardware implementation
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val jump = new Area {
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val sortedByStage = jumpInfos.sortWith((a, b) => {
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(pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) ||
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(pipeline.indexOf(a.stage) == pipeline.indexOf(b.stage) && a.priority > b.priority)
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})
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val valids = sortedByStage.map(_.interface.valid)
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val pcs = sortedByStage.map(_.interface.payload)
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val pcLoad = Flow(UInt(32 bits))
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pcLoad.valid := jumpInfos.map(_.interface.valid).orR
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pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs)
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}
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def flush = jump.pcLoad.valid
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class PcFetch extends Area{
|
||||
val output = Stream(UInt(32 bits))
|
||||
}
|
||||
|
||||
val fetchPc = if(relaxedPcCalculation) new PcFetch {
|
||||
//PC calculation without Jump
|
||||
val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
|
||||
val pcPlus4 = pcReg + 4
|
||||
if (keepPcPlus4) KeepAttribute(pcPlus4)
|
||||
when(output.fire) {
|
||||
pcReg := pcPlus4
|
||||
}
|
||||
|
||||
//Realign
|
||||
if(compressedGen){
|
||||
when(output.fire){
|
||||
pcReg(1 downto 0) := 0
|
||||
}
|
||||
}
|
||||
|
||||
//application of the selected jump request
|
||||
when(jump.pcLoad.valid) {
|
||||
pcReg := jump.pcLoad.payload
|
||||
}
|
||||
|
||||
output.valid := RegNext(True) init (False) // && !jump.pcLoad.valid
|
||||
output.payload := pcReg
|
||||
} else new PcFetch{
|
||||
//PC calculation without Jump
|
||||
val pcReg = Reg(UInt(32 bits)) init(resetVector) addAttribute(Verilator.public)
|
||||
val inc = RegInit(False)
|
||||
|
||||
val pc = pcReg + (inc ## B"00").asUInt
|
||||
val samplePcNext = False
|
||||
|
||||
when(jump.pcLoad.valid) {
|
||||
inc := False
|
||||
samplePcNext := True
|
||||
pc := jump.pcLoad.payload
|
||||
}
|
||||
|
||||
|
||||
when(output.fire){
|
||||
inc := True
|
||||
samplePcNext := True
|
||||
}
|
||||
|
||||
|
||||
when(samplePcNext) {
|
||||
pcReg := pc
|
||||
}
|
||||
|
||||
if(compressedGen) {
|
||||
when(output.fire) {
|
||||
pcReg(1 downto 0) := 0
|
||||
when(pc(1)){
|
||||
inc := True
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
output.valid := RegNext(True) init (False)
|
||||
output.payload := pc
|
||||
}
|
||||
|
||||
val decodePc = ifGen(decodePcGen)(new Area {
|
||||
//PC calculation without Jump
|
||||
val pcReg = Reg(UInt(32 bits)) init (resetVector) addAttribute (Verilator.public)
|
||||
val pcPlus = if(compressedGen)
|
||||
pcReg + ((decode.input(IS_RVC)) ? U(2) | U(4))
|
||||
else
|
||||
pcReg + 4
|
||||
|
||||
if (keepPcPlus4) KeepAttribute(pcPlus)
|
||||
when(decode.arbitration.isFiring) {
|
||||
pcReg := pcPlus
|
||||
}
|
||||
|
||||
//application of the selected jump request
|
||||
when(jump.pcLoad.valid) {
|
||||
pcReg := jump.pcLoad.payload
|
||||
}
|
||||
})
|
||||
|
||||
|
||||
val iBusCmd = new Area {
|
||||
def input = fetchPc.output
|
||||
|
||||
val output = input.continueWhen(iBus.cmd.fire)
|
||||
val cmd = new Area {
|
||||
import iBusCmd._
|
||||
output << input.continueWhen(iBus.cmd.fire)
|
||||
|
||||
//Avoid sending to many iBus cmd
|
||||
val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
|
||||
|
|
@ -280,26 +157,14 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
|
|||
iBus.cmd.pc := input.payload(31 downto 2) @@ "00"
|
||||
}
|
||||
|
||||
case class FetchRsp() extends Bundle {
|
||||
val pc = UInt(32 bits)
|
||||
val rsp = IBusSimpleRsp()
|
||||
val isRvc = Bool
|
||||
}
|
||||
|
||||
def recursive[T](that : T,depth : Int, func : (T) => T) : T = depth match {
|
||||
case 0 => that
|
||||
case _ => recursive(func(that), depth -1, func)
|
||||
}
|
||||
|
||||
val iBusRsp = new Area {
|
||||
val inputFirstStage = if(relaxedPcCalculation) iBusCmd.output.m2sPipe(flush) else iBusCmd.output.m2sPipe().throwWhen(flush)
|
||||
val input = recursive[Stream[UInt]](inputFirstStage, cmdToRspStageCount - 1, x => x.m2sPipe(flush))//iBusCmd.output.m2sPipe(flush)// ASYNC .throwWhen(flush)
|
||||
|
||||
val rsp = new Area {
|
||||
import iBusRsp._
|
||||
//Manage flush for iBus transactions in flight
|
||||
val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
|
||||
discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt
|
||||
when(flush) {
|
||||
discardCounter := (if(relaxedPcCalculation) iBusCmd.pendingCmdNext else iBusCmd.pendingCmd - iBus.rsp.fire.asUInt)
|
||||
discardCounter := (if(relaxedPcCalculation) cmd.pendingCmdNext else cmd.pendingCmd - iBus.rsp.fire.asUInt)
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -314,94 +179,8 @@ class IBusSimplePlugin(interfaceKeepData : Boolean, catchAccessFault : Boolean,
|
|||
fetchRsp.rsp.error.clearWhen(!rspBuffer.io.pop.valid) //Avoid interference with instruction injection from the debug plugin
|
||||
|
||||
|
||||
def outputGen = StreamJoin(Seq(input, rspBuffer.io.pop), fetchRsp)
|
||||
val output = if(rspStageGen) outputGen.m2sPipe(flush) else outputGen
|
||||
}
|
||||
|
||||
val decompressor = ifGen(decodePcGen)(new Area{
|
||||
def input = iBusRsp.output
|
||||
val output = Stream(FetchRsp())
|
||||
|
||||
val bufferValid = RegInit(False)
|
||||
val bufferError = Reg(Bool)
|
||||
val bufferData = Reg(Bits(16 bits))
|
||||
|
||||
val raw = Mux(
|
||||
sel = bufferValid,
|
||||
whenTrue = input.rsp.inst(15 downto 0) ## bufferData,
|
||||
whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0))
|
||||
)
|
||||
val isRvc = raw(1 downto 0) =/= 3
|
||||
val decompressed = RvcDecompressor(raw(15 downto 0))
|
||||
output.valid := isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))
|
||||
output.pc := input.pc
|
||||
output.isRvc := isRvc
|
||||
output.rsp.inst := isRvc ? decompressed | raw
|
||||
output.rsp.error := (bufferValid && bufferError) || (input.valid && input.rsp.error && (!isRvc || (isRvc && !bufferValid)))
|
||||
input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready))
|
||||
|
||||
|
||||
bufferValid clearWhen(output.fire)
|
||||
when(input.ready){
|
||||
when(input.valid) {
|
||||
bufferValid := !(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1))
|
||||
bufferError := input.rsp.error
|
||||
bufferData := input.rsp.inst(31 downto 16)
|
||||
}
|
||||
}
|
||||
bufferValid.clearWhen(flush)
|
||||
})
|
||||
|
||||
def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that
|
||||
val injector = new Area {
|
||||
val inputBeforeHalt = condApply(if(decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(flush))
|
||||
val input = inputBeforeHalt.haltWhen(fetcherHalt)
|
||||
val stage = input.m2sPipe(flush || decode.arbitration.isRemoved)
|
||||
|
||||
if(decodePcGen){
|
||||
decodeNextPcValid := True
|
||||
decodeNextPc := decodePc.pcReg
|
||||
}else {
|
||||
decodeNextPcValid := RegNext(inputBeforeHalt.isStall)
|
||||
decodeNextPc := decode.input(PC)
|
||||
}
|
||||
|
||||
stage.ready := !decode.arbitration.isStuck
|
||||
decode.arbitration.isValid := stage.valid
|
||||
decode.insert(PC) := (if(decodePcGen) decodePc.pcReg else stage.pc)
|
||||
decode.insert(INSTRUCTION) := stage.rsp.inst
|
||||
decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), input.rsp.inst)
|
||||
decode.insert(INSTRUCTION_READY) := True
|
||||
if(compressedGen) decode.insert(IS_RVC) := stage.isRvc
|
||||
|
||||
if(catchAccessFault){
|
||||
decodeExceptionPort.valid := decode.arbitration.isValid && stage.rsp.error
|
||||
decodeExceptionPort.code := 1
|
||||
decodeExceptionPort.badAddr := decode.input(PC)
|
||||
}
|
||||
|
||||
prediction match {
|
||||
case `NONE` =>
|
||||
case `STATIC` => {
|
||||
val imm = IMM(decode.input(INSTRUCTION))
|
||||
|
||||
val conditionalBranchPrediction = (prediction match {
|
||||
case `STATIC` => imm.b_sext.msb
|
||||
//case `DYNAMIC` => input(HISTORY_LINE).history.msb
|
||||
})
|
||||
decodePrediction.cmd.hadBranch := decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL || (decode.input(BRANCH_CTRL) === BranchCtrlEnum.B && conditionalBranchPrediction)
|
||||
|
||||
predictionJumpInterface.valid := decodePrediction.cmd.hadBranch && decode.arbitration.isFiring //TODO OH Doublon de priorité
|
||||
predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt
|
||||
|
||||
|
||||
// if(catchAddressMisaligned) {
|
||||
// predictionExceptionPort.valid := input(INSTRUCTION_READY) && input(PREDICTION_HAD_BRANCHED) && arbitration.isValid && predictionJumpInterface.payload(1 downto 0) =/= 0
|
||||
// predictionExceptionPort.code := 0
|
||||
// predictionExceptionPort.badAddr := predictionJumpInterface.payload
|
||||
// }
|
||||
}
|
||||
}
|
||||
val join = StreamJoin(Seq(input, rspBuffer.io.pop), fetchRsp)
|
||||
output << (if(rspStageGen) join.m2sPipeWithFlush(flush) else join)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -95,11 +95,12 @@ object RvcDecompressor{
|
|||
|
||||
object StreamVexPimper{
|
||||
implicit class StreamFlushPimper[T <: Data](pimped : Stream[T]){
|
||||
def m2sPipe(flush : Bool, collapsBubble : Boolean = true): Stream[T] = {
|
||||
def m2sPipeWithFlush(flush : Bool, discardInput : Boolean = true, collapsBubble : Boolean = true): Stream[T] = {
|
||||
val ret = cloneOf(pimped)
|
||||
|
||||
val rValid = RegInit(False)
|
||||
val rData = Reg(pimped.dataType)
|
||||
if(!discardInput) rValid.clearWhen(flush)
|
||||
|
||||
pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready
|
||||
|
||||
|
|
@ -111,7 +112,7 @@ object StreamVexPimper{
|
|||
ret.valid := rValid
|
||||
ret.payload := rData
|
||||
|
||||
rValid.clearWhen(flush)
|
||||
if(discardInput) rValid.clearWhen(flush)
|
||||
|
||||
ret
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue