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VexRiscv
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Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 

# Conflicts:
#	src/main/scala/vexriscv/plugin/CsrPlugin.scala
This commit is contained in:
Dolu1990 2020-11-16 12:37:48 +01:00
parent dae633aa7d
commit e0ae46e794
1 changed files with 2 additions and 12 deletions
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14
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -1010,18 +1010,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val readData = Bits(32 bits)
val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid
val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && !readDataRegValid
//arbitration.isStuckByOthers, in case of the hazardPlugin is in the executeStage
// def readDataReg = memory.input(REGFILE_WRITE_DATA) //PIPE OPT
// val readDataRegValid = Reg(Bool) setWhen(arbitration.isValid) clearWhen(!arbitration.isStuck)
// val writeDataEnable = input(INSTRUCTION)(13) ? writeSrc | B"xFFFFFFFF"
// val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
// False -> writeSrc,
// True -> Mux(input(INSTRUCTION)(12), ~writeSrc, writeSrc)
// )
val writeEnable = writeInstruction && !arbitration.isStuck
val readEnable = readInstruction && !arbitration.isStuck
val readToWriteData = CombInit(readData)
val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(