Handle ClockDomain improvements
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@ -65,12 +65,12 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
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val debugBmbAccessSource = Handle[BmbAccessCapabilities]
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val debugBmbAccessRequirements = Handle[BmbAccessParameter]
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def enableDebugBmb(debugCd : ClockDomainResetGenerator, resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.rework{
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this.debugClockDomain.load(debugCd.outputClockDomain)
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def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGenerator, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{
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this.debugClockDomain.load(debugCd)
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val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH)
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debugAskReset.loadNothing()
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withDebug.load(DEBUG_BMB)
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val slaveModel = debugCd.outputClockDomain on interconnectSmp.addSlave(
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val slaveModel = debugCd on interconnectSmp.addSlave(
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accessSource = debugBmbAccessSource,
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accessCapabilities = debugBmbAccessSource.derivate(DebugExtensionBus.getBmbAccessParameter(_)),
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accessRequirements = debugBmbAccessRequirements,
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@ -81,7 +81,6 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
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if(debugMaster != null) interconnectSmp.addConnection(debugMaster.bus, debugBmb)
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}
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val jtag = Handle(withDebug.get == DEBUG_JTAG generate slave(Jtag()))
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val jtagInstructionCtrl = withDebug.produce(withDebug.get == DEBUG_JTAG_CTRL generate JtagTapInstructionCtrl())
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val debugBus = withDebug.produce(withDebug.get == DEBUG_BUS generate DebugExtensionBus())
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@ -76,7 +76,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
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cpu.dBus -> List(dBusCoherent.bmb)
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)
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cpu.enableDebugBmb(
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debugCd = debugCd,
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debugCd = debugCd.outputClockDomain,
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resetCd = systemCd,
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mapping = SizeMapping(cpuId*0x1000, 0x1000)
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)
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