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CsrPlugin now make SATP write rescheduling the next instruction

This commit is contained in:
Charles Papon 2019-12-09 22:23:07 +01:00
parent 744b040c70
commit e25dfb4fbf
1 changed files with 15 additions and 0 deletions
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15
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -334,6 +334,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
var exceptionPendings : Vec[Bool] = null var exceptionPendings : Vec[Bool] = null
override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage)) override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage))
var redoInterface : Flow[UInt] = null
var jumpInterface : Flow[UInt] = null var jumpInterface : Flow[UInt] = null
var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null
var externalInterruptS : Bool = null var externalInterruptS : Bool = null
@ -430,6 +431,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
jumpInterface.valid := False jumpInterface.valid := False
jumpInterface.payload.assignDontCare() jumpInterface.payload.assignDontCare()
if(supervisorGen) {
redoInterface = pcManagerService.createJumpInterface(pipeline.execute)
redoInterface.valid := False
redoInterface.payload.assignDontCare()
}
exceptionPendings = Vec(Bool, pipeline.stages.length) exceptionPendings = Vec(Bool, pipeline.stages.length)
timerInterrupt = in Bool() setName("timerInterrupt") timerInterrupt = in Bool() setName("timerInterrupt")
externalInterrupt = in Bool() setName("externalInterrupt") externalInterrupt = in Bool() setName("externalInterrupt")
@ -619,6 +627,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode) scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode)
sbadaddrAccess(CSR.SBADADDR, stval) sbadaddrAccess(CSR.SBADADDR, stval)
satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN)
if(supervisorGen) onWrite(CSR.SATP){
execute.arbitration.flushNext := True
redoInterface.valid := True
redoInterface.payload := execute.input(PC) + 4
}
} }
} }