CsrPlugin now make SATP write rescheduling the next instruction
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@ -334,6 +334,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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var exceptionPendings : Vec[Bool] = null
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override def isExceptionPending(stage : Stage): Bool = exceptionPendings(pipeline.stages.indexOf(stage))
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var redoInterface : Flow[UInt] = null
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var jumpInterface : Flow[UInt] = null
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var timerInterrupt, externalInterrupt, softwareInterrupt : Bool = null
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var externalInterruptS : Bool = null
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@ -430,6 +431,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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jumpInterface.valid := False
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jumpInterface.payload.assignDontCare()
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if(supervisorGen) {
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redoInterface = pcManagerService.createJumpInterface(pipeline.execute)
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redoInterface.valid := False
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redoInterface.payload.assignDontCare()
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}
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exceptionPendings = Vec(Bool, pipeline.stages.length)
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timerInterrupt = in Bool() setName("timerInterrupt")
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externalInterrupt = in Bool() setName("externalInterrupt")
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@ -619,6 +627,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode)
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sbadaddrAccess(CSR.SBADADDR, stval)
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satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN)
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if(supervisorGen) onWrite(CSR.SATP){
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execute.arbitration.flushNext := True
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redoInterface.valid := True
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redoInterface.payload := execute.input(PC) + 4
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}
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}
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}
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