Hardware/VexRiscv
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MMU pass all test, need to and SUM and MXR and it's all ok

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This commit is contained in:
Dolu1990 2019-03-22 14:52:49 +01:00
parent 2b458fc642
commit e4cdc2397a
9 changed files with 517 additions and 406 deletions
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2
src/main/scala/vexriscv/Pipeline.scala
View file

@ -119,7 +119,7 @@ trait Pipeline {
inputDefault := stage.inserts(key)
} else {
val stageBefore = stages(stageIndex - 1)
inputDefault := RegNextWhen(stageBefore.output(key), !stage.arbitration.isStuck).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")
inputDefault := RegNextWhen(stageBefore.output(key), stage.dontSample.getOrElse(key, Nil).foldLeft(!stage.arbitration.isStuck)(_ && !_)).setName(s"${stageBefore.getName()}_to_${stage.getName()}_${key.getName()}")
}
}
}

3
src/main/scala/vexriscv/Stage.scala
View file

@ -4,6 +4,7 @@ import spinal.core._
import spinal.lib._
import scala.collection.mutable
import scala.collection.mutable.ArrayBuffer
class Stageable[T <: Data](_dataType : => T) extends HardType[T](_dataType) with Nameable{
@ -68,6 +69,8 @@ class Stage() extends Area{
val inputsDefault = mutable.HashMap[Stageable[Data],Data]()
val outputsDefault = mutable.HashMap[Stageable[Data],Data]()
val dontSample = mutable.HashMap[Stageable[_], ArrayBuffer[Bool]]()
def inputInit[T <: BaseType](stageable : Stageable[T],initValue : T) =
Component.current.addPrePopTask(() => inputsDefault(stageable.asInstanceOf[Stageable[Data]]).asInstanceOf[T].getDrivingReg.init(initValue))
}

18
src/main/scala/vexriscv/plugin/CsrPlugin.scala
View file

@ -672,6 +672,9 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
when(exceptionValidsRegs.orR){
fetcher.haltIt()
}
//Avoid the PC register of the last stage to change durring an exception handleing (Used to fill Xepc)
stages.last.dontSample.getOrElseUpdate(PC, ArrayBuffer[Bool]()) += exceptionValids.last
} else null
@ -744,18 +747,6 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
trapCause := exceptionPortCtrl.exceptionContext.code
}
when(exception || interruptJump){
switch(privilege){
if(supervisorGen) is(1) {
sepc := mepcCaptureStage.input(PC)
}
is(3){
mepc := mepcCaptureStage.input(PC)
}
}
}
val xtvec = Xtvec().assignDontCare()
switch(targetPrivilege){
if(supervisorGen) is(1) { xtvec := supervisorCsr.stvec }
@ -768,6 +759,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
beforeLastStage.arbitration.flushAll := True
privilege := targetPrivilege
switch(targetPrivilege){
if(supervisorGen) is(1) {
sstatus.SIE := False
@ -775,6 +767,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
sstatus.SPP := privilege(0 downto 0)
scause.interrupt := !hadException
scause.exceptionCode := trapCause
sepc := mepcCaptureStage.input(PC)
if (exceptionPortCtrl != null) {
stval := exceptionPortCtrl.exceptionContext.badAddr
}
@ -786,6 +779,7 @@ class CsrPlugin(config: CsrPluginConfig) extends Plugin[VexRiscv] with Exception
mstatus.MPP := privilege
mcause.interrupt := !hadException
mcause.exceptionCode := trapCause
mepc := mepcCaptureStage.input(PC)
if(exceptionPortCtrl != null) {
mtval := exceptionPortCtrl.exceptionContext.badAddr
}

3
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View file

@ -377,6 +377,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
memoryExceptionPort.valid := True
memoryExceptionPort.code := (input(INSTRUCTION)(5) ? U(15) | U(13)).resized
}
arbitration.flushAll setWhen(redoBranch.valid)
}
when(!(arbitration.isValid && input(MEMORY_ENABLE) && (Bool(cmdStage != rspStage) || !arbitration.isStuckByOthers))){
@ -384,7 +386,6 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
if(memoryTranslatorPortConfig != null) redoBranch.valid := False
}
arbitration.flushAll setWhen(redoBranch.valid)
}

4
src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
View file

@ -303,9 +303,9 @@ class IBusSimplePlugin(resetVector : BigInt,
redoRequired setWhen( stages.last.input.valid && mmu.joinCtx.refilling)
redoBranch.valid := redoRequired && iBusRsp.readyForError
redoBranch.payload := stages.last.input.payload
decode.arbitration.flushAll setWhen(redoBranch.valid)
}
decode.arbitration.flushAll setWhen(redoBranch.valid)
if(catchSomething){
decodeExceptionPort.code.assignDontCare()
@ -322,7 +322,7 @@ class IBusSimplePlugin(resetVector : BigInt,
exceptionDetected := True
}
}
decodeExceptionPort.valid := exceptionDetected && iBusRsp.readyForError
decodeExceptionPort.valid := exceptionDetected && iBusRsp.readyForError && !fetcherHalt
}
}
}

576
src/test/cpp/raw/mmu/build/mmu.asm
View file

@ -4,295 +4,317 @@ build/mmu.elf: file format elf32-littleriscv
Disassembly of section .crt_section:
80000000 <ROM_SUPER_0>:
80000000: 0280006f j 80000028 <_start>
80000004: 00000013 nop
80000008: 00000013 nop
8000000c: 00000013 nop
80000010: 00000013 nop
80000014: 00000013 nop
80000018: 00000013 nop
8000001c: 00000013 nop
80000000 <_start>:
80000000: 00000e93 li t4,0
80000004: 00000097 auipc ra,0x0
80000008: 3e808093 addi ra,ra,1000 # 800003ec <trap>
8000000c: 30509073 csrw mtvec,ra
80000020 <trap_entry>:
80000020: 1f80006f j 80000218 <fail>
80000024: 30200073 mret
80000010 <test1>:
80000010: 00100e13 li t3,1
80000014: 00007097 auipc ra,0x7
80000018: fec08093 addi ra,ra,-20 # 80007000 <ROM_2>
8000001c: 27262137 lui sp,0x27262
80000020: 52410113 addi sp,sp,1316 # 27262524 <_start-0x58d9dadc>
80000024: 0040a083 lw ra,4(ra)
80000028: 38209e63 bne ra,sp,800003c4 <fail>
80000028 <_start>:
80000028: 00000097 auipc ra,0x0
8000002c: 1f008093 addi ra,ra,496 # 80000218 <fail>
80000030: 30509073 csrw mtvec,ra
80000034: 10509073 csrw stvec,ra
8000002c <test2>:
8000002c: 00200e13 li t3,2
80000030: 00000097 auipc ra,0x0
80000034: 02008093 addi ra,ra,32 # 80000050 <test3>
80000038: 34109073 csrw mepc,ra
8000003c: 000020b7 lui ra,0x2
80000040: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800>
80000044: 30009073 csrw mstatus,ra
80000048: 30200073 mret
8000004c: 3780006f j 800003c4 <fail>
80000038 <test1>:
80000038: 00100e13 li t3,1
8000003c: 00007097 auipc ra,0x7
80000040: fc408093 addi ra,ra,-60 # 80007000 <ROM_2>
80000044: 27262137 lui sp,0x27262
80000048: 52410113 addi sp,sp,1316 # 27262524 <ROM_SUPER_0-0x58d9dadc>
8000004c: 0040a083 lw ra,4(ra)
80000050: 1c209463 bne ra,sp,80000218 <fail>
80000050 <test3>:
80000050: 00300e13 li t3,3
80000054: 000010b7 lui ra,0x1
80000058: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800>
8000005c: 30009073 csrw mstatus,ra
80000060: 00000097 auipc ra,0x0
80000064: 01408093 addi ra,ra,20 # 80000074 <test4>
80000068: 34109073 csrw mepc,ra
8000006c: 30200073 mret
80000070: 3540006f j 800003c4 <fail>
80000054 <test2>:
80000054: 00200e13 li t3,2
80000058: 00000097 auipc ra,0x0
8000005c: 02008093 addi ra,ra,32 # 80000078 <test3>
80000060: 34109073 csrw mepc,ra
80000064: 000020b7 lui ra,0x2
80000068: 80008093 addi ra,ra,-2048 # 1800 <ROM_SUPER_0-0x7fffe800>
8000006c: 30009073 csrw mstatus,ra
80000070: 30200073 mret
80000074: 1a40006f j 80000218 <fail>
80000074 <test4>:
80000074: 00400e13 li t3,4
80000078: 00008097 auipc ra,0x8
8000007c: f8808093 addi ra,ra,-120 # 80008000 <ROM_3>
80000080: 37363137 lui sp,0x37363
80000084: 53410113 addi sp,sp,1332 # 37363534 <_start-0x48c9cacc>
80000088: 0040a083 lw ra,4(ra)
8000008c: 32209c63 bne ra,sp,800003c4 <fail>
80000078 <test3>:
80000078: 00300e13 li t3,3
8000007c: 000010b7 lui ra,0x1
80000080: 80008093 addi ra,ra,-2048 # 800 <ROM_SUPER_0-0x7ffff800>
80000084: 30009073 csrw mstatus,ra
80000088: 00000097 auipc ra,0x0
8000008c: 01408093 addi ra,ra,20 # 8000009c <test4>
80000090: 34109073 csrw mepc,ra
80000094: 30200073 mret
80000098: 1800006f j 80000218 <fail>
80000090 <test5>:
80000090: 00500e13 li t3,5
80000094: 00001097 auipc ra,0x1
80000098: 76c08093 addi ra,ra,1900 # 80001800 <MMU_TABLE_0+0x800>
8000009c: 00002117 auipc sp,0x2
800000a0: f6410113 addi sp,sp,-156 # 80002000 <MMU_TABLE_1>
800000a4: 00215113 srli sp,sp,0x2
800000a8: 01116113 ori sp,sp,17
800000ac: 0020a023 sw sp,0(ra)
800000b0: 00002097 auipc ra,0x2
800000b4: f5008093 addi ra,ra,-176 # 80002000 <MMU_TABLE_1>
800000b8: 80000137 lui sp,0x80000
800000bc: 00215113 srli sp,sp,0x2
800000c0: 01f16113 ori sp,sp,31
800000c4: 0020a023 sw sp,0(ra)
800000c8: 00500e13 li t3,5
800000cc: 00002097 auipc ra,0x2
800000d0: 83408093 addi ra,ra,-1996 # 80001900 <MMU_TABLE_0+0x900>
800000d4: 00003117 auipc sp,0x3
800000d8: f2c10113 addi sp,sp,-212 # 80003000 <MMU_TABLE_2>
800000dc: 00215113 srli sp,sp,0x2
800000e0: 01116113 ori sp,sp,17
800000e4: 0020a023 sw sp,0(ra)
800000e8: 00003097 auipc ra,0x3
800000ec: f4008093 addi ra,ra,-192 # 80003028 <MMU_TABLE_2+0x28>
800000f0: 00009117 auipc sp,0x9
800000f4: f1010113 addi sp,sp,-240 # 80009000 <ROM_4>
800000f8: 00215113 srli sp,sp,0x2
800000fc: 01f16113 ori sp,sp,31
80000100: 0020a023 sw sp,0(ra)
80000104: 00003097 auipc ra,0x3
80000108: f3c08093 addi ra,ra,-196 # 80003040 <MMU_TABLE_2+0x40>
8000010c: 0000a117 auipc sp,0xa
80000110: ef410113 addi sp,sp,-268 # 8000a000 <ROM_5>
80000114: 00215113 srli sp,sp,0x2
80000118: 01316113 ori sp,sp,19
8000011c: 0020a023 sw sp,0(ra)
80000120: 00003097 auipc ra,0x3
80000124: f2408093 addi ra,ra,-220 # 80003044 <MMU_TABLE_2+0x44>
80000128: 0000a117 auipc sp,0xa
8000012c: ed810113 addi sp,sp,-296 # 8000a000 <ROM_5>
80000130: 00215113 srli sp,sp,0x2
80000134: 01716113 ori sp,sp,23
80000138: 0020a023 sw sp,0(ra)
8000013c: 00003097 auipc ra,0x3
80000140: f0c08093 addi ra,ra,-244 # 80003048 <MMU_TABLE_2+0x48>
80000144: 0000a117 auipc sp,0xa
80000148: ebc10113 addi sp,sp,-324 # 8000a000 <ROM_5>
8000014c: 00215113 srli sp,sp,0x2
80000150: 01916113 ori sp,sp,25
80000154: 0020a023 sw sp,0(ra)
80000158: 00003097 auipc ra,0x3
8000015c: ef408093 addi ra,ra,-268 # 8000304c <MMU_TABLE_2+0x4c>
80000160: 0000a117 auipc sp,0xa
80000164: ea010113 addi sp,sp,-352 # 8000a000 <ROM_5>
80000168: 00215113 srli sp,sp,0x2
8000016c: 01b16113 ori sp,sp,27
80000170: 0020a023 sw sp,0(ra)
80000174: 00500e13 li t3,5
80000178: 00002097 auipc ra,0x2
8000017c: 88808093 addi ra,ra,-1912 # 80001a00 <MMU_TABLE_0+0xa00>
80000180: 00000117 auipc sp,0x0
80000184: e8010113 addi sp,sp,-384 # 80000000 <_start>
80000188: 00215113 srli sp,sp,0x2
8000018c: 01f16113 ori sp,sp,31
80000190: 0020a023 sw sp,0(ra)
80000194: 00500e13 li t3,5
80000198: 00002097 auipc ra,0x2
8000019c: 96808093 addi ra,ra,-1688 # 80001b00 <MMU_TABLE_0+0xb00>
800001a0: 0000a023 sw zero,0(ra)
800001a4: 00001097 auipc ra,0x1
800001a8: e5c08093 addi ra,ra,-420 # 80001000 <MMU_TABLE_0>
800001ac: 00c0d093 srli ra,ra,0xc
800001b0: 80000137 lui sp,0x80000
800001b4: 0020e0b3 or ra,ra,sp
800001b8: 18009073 csrw satp,ra
8000009c <test4>:
8000009c: 00400e13 li t3,4
800000a0: 00008097 auipc ra,0x8
800000a4: f6008093 addi ra,ra,-160 # 80008000 <ROM_3>
800000a8: 37363137 lui sp,0x37363
800000ac: 53410113 addi sp,sp,1332 # 37363534 <ROM_SUPER_0-0x48c9cacc>
800000b0: 0040a083 lw ra,4(ra)
800000b4: 16209263 bne ra,sp,80000218 <fail>
800001bc <test6>:
800001bc: 00600e13 li t3,6
800001c0: 9000a0b7 lui ra,0x9000a
800001c4: 00808093 addi ra,ra,8 # 9000a008 <ROM_7+0xfffe008>
800001c8: 4b4a5137 lui sp,0x4b4a5
800001cc: 94810113 addi sp,sp,-1720 # 4b4a4948 <_start-0x34b5b6b8>
800001d0: 0000a083 lw ra,0(ra)
800001d4: 1e209863 bne ra,sp,800003c4 <fail>
800000b8 <test5>:
800000b8: 00500e13 li t3,5
800000bc: 00001097 auipc ra,0x1
800000c0: 74408093 addi ra,ra,1860 # 80001800 <MMU_TABLE_0+0x800>
800000c4: 00002117 auipc sp,0x2
800000c8: f3c10113 addi sp,sp,-196 # 80002000 <MMU_TABLE_1>
800000cc: 00215113 srli sp,sp,0x2
800000d0: 01116113 ori sp,sp,17
800000d4: 0020a023 sw sp,0(ra)
800000d8: 00002097 auipc ra,0x2
800000dc: f2808093 addi ra,ra,-216 # 80002000 <MMU_TABLE_1>
800000e0: 80000137 lui sp,0x80000
800000e4: 00215113 srli sp,sp,0x2
800000e8: 01f16113 ori sp,sp,31
800000ec: 0020a023 sw sp,0(ra)
800000f0: 00500e13 li t3,5
800000f4: 00002097 auipc ra,0x2
800000f8: 80c08093 addi ra,ra,-2036 # 80001900 <MMU_TABLE_0+0x900>
800000fc: 00003117 auipc sp,0x3
80000100: f0410113 addi sp,sp,-252 # 80003000 <MMU_TABLE_2>
80000104: 00215113 srli sp,sp,0x2
80000108: 01116113 ori sp,sp,17
8000010c: 0020a023 sw sp,0(ra)
80000110: 00003097 auipc ra,0x3
80000114: f1808093 addi ra,ra,-232 # 80003028 <MMU_TABLE_2+0x28>
80000118: 00009117 auipc sp,0x9
8000011c: ee810113 addi sp,sp,-280 # 80009000 <ROM_4>
80000120: 00215113 srli sp,sp,0x2
80000124: 01f16113 ori sp,sp,31
80000128: 0020a023 sw sp,0(ra)
8000012c: 00500e13 li t3,5
80000130: 00002097 auipc ra,0x2
80000134: 8d008093 addi ra,ra,-1840 # 80001a00 <MMU_TABLE_0+0xa00>
80000138: 00000117 auipc sp,0x0
8000013c: ec810113 addi sp,sp,-312 # 80000000 <ROM_SUPER_0>
80000140: 00215113 srli sp,sp,0x2
80000144: 01f16113 ori sp,sp,31
80000148: 0020a023 sw sp,0(ra)
8000014c: 00001097 auipc ra,0x1
80000150: eb408093 addi ra,ra,-332 # 80001000 <MMU_TABLE_0>
80000154: 00c0d093 srli ra,ra,0xc
80000158: 80000137 lui sp,0x80000
8000015c: 0020e0b3 or ra,ra,sp
80000160: 18009073 csrw satp,ra
800001d8 <test7>:
800001d8: 00700e13 li t3,7
800001dc: 9000a0b7 lui ra,0x9000a
800001e0: 36008093 addi ra,ra,864 # 9000a360 <ROM_7+0xfffe360>
800001e4: aaee0137 lui sp,0xaaee0
800001e8: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
800001ec: 0020a023 sw sp,0(ra)
800001f0: 0000a083 lw ra,0(ra)
800001f4: 1c209863 bne ra,sp,800003c4 <fail>
80000164 <test6>:
80000164: 00600e13 li t3,6
80000168: 9000a0b7 lui ra,0x9000a
8000016c: 00808093 addi ra,ra,8 # 9000a008 <ROM_7+0xfffe008>
80000170: 4b4a5137 lui sp,0x4b4a5
80000174: 94810113 addi sp,sp,-1720 # 4b4a4948 <ROM_SUPER_0-0x34b5b6b8>
80000178: 0000a083 lw ra,0(ra)
8000017c: 08209e63 bne ra,sp,80000218 <fail>
80000180 <test7>:
80000180: 00700e13 li t3,7
80000184: 9000a0b7 lui ra,0x9000a
80000188: 36008093 addi ra,ra,864 # 9000a360 <ROM_7+0xfffe360>
8000018c: aaee0137 lui sp,0xaaee0
80000190: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
80000194: 0020a023 sw sp,0(ra)
80000198: 0000a083 lw ra,0(ra)
8000019c: 06209e63 bne ra,sp,80000218 <fail>
800001a0 <test8>:
800001a0: 00800e13 li t3,8
800001a4: 2000c097 auipc ra,0x2000c
800001a8: e6008093 addi ra,ra,-416 # a000c004 <ROM_7+0x20000004>
800001ac: 77767137 lui sp,0x77767
800001b0: 57410113 addi sp,sp,1396 # 77767574 <ROM_SUPER_0-0x8898a8c>
800001b4: 0000a083 lw ra,0(ra)
800001b8: 06209063 bne ra,sp,80000218 <fail>
800001bc <test9>:
800001bc: 00900e13 li t3,9
800001c0: a000a0b7 lui ra,0xa000a
800001c4: 36008093 addi ra,ra,864 # a000a360 <ROM_7+0x1fffe360>
800001c8: aaee0137 lui sp,0xaaee0
800001cc: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
800001d0: 0020a023 sw sp,0(ra)
800001d4: 0000a083 lw ra,0(ra)
800001d8: 04209063 bne ra,sp,80000218 <fail>
800001dc <test10>:
800001dc: 00a00e13 li t3,10
800001e0: 18005073 csrwi satp,0
800001e4: 00009097 auipc ra,0x9
800001e8: 17c08093 addi ra,ra,380 # 80009360 <ROM_4+0x360>
800001ec: aaee0137 lui sp,0xaaee0
800001f0: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
800001f4: 0000a083 lw ra,0(ra)
800001f8: 02209063 bne ra,sp,80000218 <fail>
800001fc: 0000a097 auipc ra,0xa
80000200: 16408093 addi ra,ra,356 # 8000a360 <ROM_5+0x360>
80000204: aaee0137 lui sp,0xaaee0
80000208: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
800001f8 <test8>:
800001f8: 00800e13 li t3,8
800001fc: 2000c097 auipc ra,0x2000c
80000200: e0808093 addi ra,ra,-504 # a000c004 <ROM_7+0x20000004>
80000204: 77767137 lui sp,0x77767
80000208: 57410113 addi sp,sp,1396 # 77767574 <_start-0x8898a8c>
8000020c: 0000a083 lw ra,0(ra)
80000210: 00209463 bne ra,sp,80000218 <fail>
80000214: 0180006f j 8000022c <pass>
80000210: 1a209a63 bne ra,sp,800003c4 <fail>
80000218 <fail>:
80000218: 18005073 csrwi satp,0
8000021c: 0040006f j 80000220 <failFence>
80000214 <test9>:
80000214: 00900e13 li t3,9
80000218: a000a0b7 lui ra,0xa000a
8000021c: 36008093 addi ra,ra,864 # a000a360 <ROM_7+0x1fffe360>
80000220: aaee0137 lui sp,0xaaee0
80000224: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
80000228: 0020a023 sw sp,0(ra)
8000022c: 0000a083 lw ra,0(ra)
80000230: 18209a63 bne ra,sp,800003c4 <fail>
80000220 <failFence>:
80000220: f0100137 lui sp,0xf0100
80000224: f2410113 addi sp,sp,-220 # f00fff24 <ROM_7+0x700f3f24>
80000228: 01c12023 sw t3,0(sp)
80000234 <test10>:
80000234: 00a00e13 li t3,10
80000238: 18005073 csrwi satp,0
8000023c: 00009097 auipc ra,0x9
80000240: 12408093 addi ra,ra,292 # 80009360 <ROM_4+0x360>
80000244: aaee0137 lui sp,0xaaee0
80000248: 00110113 addi sp,sp,1 # aaee0001 <ROM_7+0x2aed4001>
8000024c: 0000a083 lw ra,0(ra)
80000250: 16209a63 bne ra,sp,800003c4 <fail>
8000022c <pass>:
8000022c: 18005073 csrwi satp,0
80000230: 0040006f j 80000234 <passFence>
80000254 <test11>:
80000254: 00b00e13 li t3,11
80000258: 0000a097 auipc ra,0xa
8000025c: 10808093 addi ra,ra,264 # 8000a360 <ROM_5+0x360>
80000260: aaee0137 lui sp,0xaaee0
80000264: 00210113 addi sp,sp,2 # aaee0002 <ROM_7+0x2aed4002>
80000268: 0000a083 lw ra,0(ra)
8000026c: 14209c63 bne ra,sp,800003c4 <fail>
80000270: 00001097 auipc ra,0x1
80000274: d9008093 addi ra,ra,-624 # 80001000 <MMU_TABLE_0>
80000278: 00c0d093 srli ra,ra,0xc
8000027c: 80000137 lui sp,0x80000
80000280: 0020e0b3 or ra,ra,sp
80000284: 18009073 csrw satp,ra
80000234 <passFence>:
80000234: f0100137 lui sp,0xf0100
80000238: f2010113 addi sp,sp,-224 # f00fff20 <ROM_7+0x700f3f20>
8000023c: 00012023 sw zero,0(sp)
80000240: 00000013 nop
80000244: 00000013 nop
80000248: 00000013 nop
8000024c: 00000013 nop
80000250: 00000013 nop
80000254: 00000013 nop
80000258: 00000013 nop
8000025c: 00000013 nop
80000260: 00000013 nop
80000264: 00000013 nop
80000268: 00000013 nop
8000026c: 00000013 nop
80000270: 00000013 nop
80000274: 00000013 nop
80000278: 00000013 nop
8000027c: 00000013 nop
80000280: 00000013 nop
80000284: 00000013 nop
80000288: 00000013 nop
8000028c: 00000013 nop
80000290: 00000013 nop
80000294: 00000013 nop
80000298: 00000013 nop
8000029c: 00000013 nop
800002a0: 00000013 nop
800002a4: 00000013 nop
800002a8: 00000013 nop
800002ac: 00000013 nop
800002b0: 00000013 nop
800002b4: 00000013 nop
800002b8: 00000013 nop
800002bc: 00000013 nop
800002c0: 00000013 nop
800002c4: 00000013 nop
800002c8: 00000013 nop
800002cc: 00000013 nop
800002d0: 00000013 nop
800002d4: 00000013 nop
800002d8: 00000013 nop
800002dc: 00000013 nop
800002e0: 00000013 nop
800002e4: 00000013 nop
800002e8: 00000013 nop
800002ec: 00000013 nop
800002f0: 00000013 nop
800002f4: 00000013 nop
800002f8: 00000013 nop
800002fc: 00000013 nop
80000300: 00000013 nop
80000304: 00000013 nop
80000308: 00000013 nop
8000030c: 00000013 nop
80000310: 00000013 nop
80000314: 00000013 nop
80000318: 00000013 nop
8000031c: 00000013 nop
80000320: 00000013 nop
80000324: 00000013 nop
80000328: 00000013 nop
8000032c: 00000013 nop
80000330: 00000013 nop
80000334: 00000013 nop
80000338: 00000013 nop
8000033c: 00000013 nop
80000340: 00000013 nop
80000344: 00000013 nop
80000348: 00000013 nop
8000034c: 00000013 nop
80000350: 00000013 nop
80000354: 00000013 nop
80000358: 00000013 nop
8000035c: 00000013 nop
80000360: 00000013 nop
80000364: 00000013 nop
80000368: 00000013 nop
8000036c: 00000013 nop
80000370: 00000013 nop
80000374: 00000013 nop
80000378: 00000013 nop
8000037c: 00000013 nop
80000380: 00000013 nop
80000384: 00000013 nop
80000388: 00000013 nop
8000038c: 00000013 nop
80000390: 00000013 nop
80000394: 00000013 nop
80000398: 00000013 nop
8000039c: 00000013 nop
800003a0: 00000013 nop
800003a4: 00000013 nop
800003a8: 00000013 nop
800003ac: 00000013 nop
800003b0: 00000013 nop
800003b4: 00000013 nop
800003b8: 00000013 nop
800003bc: 00000013 nop
800003c0: 00000013 nop
800003c4: 00000013 nop
800003c8: 00000013 nop
800003cc: 00000013 nop
800003d0: 00000013 nop
800003d4: 00000013 nop
800003d8: 00000013 nop
800003dc: 00000013 nop
800003e0: 00000013 nop
800003e4: 00000013 nop
800003e8: 00000013 nop
800003ec: 00000013 nop
800003f0: 00000013 nop
800003f4: 00000013 nop
800003f8: 00000013 nop
800003fc: 00000013 nop
80000288 <test12>:
80000288: 00c00e13 li t3,12
8000028c: 00100e93 li t4,1
80000290: 00000f17 auipc t5,0x0
80000294: 010f0f13 addi t5,t5,16 # 800002a0 <test13>
80000298: 00000073 ecall
8000029c: 1280006f j 800003c4 <fail>
800002a0 <test13>:
800002a0: 00d00e13 li t3,13
800002a4: 00000f17 auipc t5,0x0
800002a8: 014f0f13 addi t5,t5,20 # 800002b8 <test14>
800002ac: b00000b7 lui ra,0xb0000
800002b0: 0080a083 lw ra,8(ra) # b0000008 <ROM_7+0x2fff4008>
800002b4: 1100006f j 800003c4 <fail>
800002b8 <test14>:
800002b8: 00e00e13 li t3,14
800002bc: 00000f17 auipc t5,0x0
800002c0: 014f0f13 addi t5,t5,20 # 800002d0 <test15>
800002c4: b00000b7 lui ra,0xb0000
800002c8: 0010a423 sw ra,8(ra) # b0000008 <ROM_7+0x2fff4008>
800002cc: 0f80006f j 800003c4 <fail>
800002d0 <test15>:
800002d0: 00f00e13 li t3,15
800002d4: 00000f17 auipc t5,0x0
800002d8: 014f0f13 addi t5,t5,20 # 800002e8 <test15_end>
800002dc: b00000b7 lui ra,0xb0000
800002e0: 00008067 ret
800002e4: 0e00006f j 800003c4 <fail>
800002e8 <test15_end>:
800002e8: 01000e13 li t3,16
800002ec: 00000e93 li t4,0
800002f0: 900100b7 lui ra,0x90010
800002f4: 00808093 addi ra,ra,8 # 90010008 <ROM_7+0x10004008>
800002f8: 5b5a6137 lui sp,0x5b5a6
800002fc: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8>
80000300: 0000a083 lw ra,0(ra)
80000304: 0c209063 bne ra,sp,800003c4 <fail>
80000308: 900110b7 lui ra,0x90011
8000030c: 00808093 addi ra,ra,8 # 90011008 <ROM_7+0x10005008>
80000310: 5b5a6137 lui sp,0x5b5a6
80000314: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8>
80000318: 0000a083 lw ra,0(ra)
8000031c: 0a209463 bne ra,sp,800003c4 <fail>
80000320: 900130b7 lui ra,0x90013
80000324: 00808093 addi ra,ra,8 # 90013008 <ROM_7+0x10007008>
80000328: 5b5a6137 lui sp,0x5b5a6
8000032c: 95810113 addi sp,sp,-1704 # 5b5a5958 <_start-0x24a5a6a8>
80000330: 0000a083 lw ra,0(ra)
80000334: 08209863 bne ra,sp,800003c4 <fail>
80000338 <test17>:
80000338: 01100e13 li t3,17
8000033c: 900110b7 lui ra,0x90011
80000340: 36008093 addi ra,ra,864 # 90011360 <ROM_7+0x10005360>
80000344: aaee0137 lui sp,0xaaee0
80000348: 00310113 addi sp,sp,3 # aaee0003 <ROM_7+0x2aed4003>
8000034c: 0020a023 sw sp,0(ra)
80000350: 0000a083 lw ra,0(ra)
80000354: 06209863 bne ra,sp,800003c4 <fail>
80000358 <test18>:
80000358: 01200e13 li t3,18
8000035c: 00000097 auipc ra,0x0
80000360: 01808093 addi ra,ra,24 # 80000374 <test18_end>
80000364: 90012137 lui sp,0x90012
80000368: 01010113 addi sp,sp,16 # 90012010 <ROM_7+0x10006010>
8000036c: 00010067 jr sp
80000370: 0540006f j 800003c4 <fail>
80000374 <test18_end>:
80000374: 00100e93 li t4,1
80000378: 00000f17 auipc t5,0x0
8000037c: 018f0f13 addi t5,t5,24 # 80000390 <test19_readTrap>
80000380: 900120b7 lui ra,0x90012
80000384: 01008093 addi ra,ra,16 # 90012010 <ROM_7+0x10006010>
80000388: 0000a083 lw ra,0(ra)
8000038c: 0380006f j 800003c4 <fail>
80000390 <test19_readTrap>:
80000390: 00000f17 auipc t5,0x0
80000394: 018f0f13 addi t5,t5,24 # 800003a8 <test19_writeTrap>
80000398: 900130b7 lui ra,0x90013
8000039c: 01008093 addi ra,ra,16 # 90013010 <ROM_7+0x10007010>
800003a0: 0010a023 sw ra,0(ra)
800003a4: 0200006f j 800003c4 <fail>
800003a8 <test19_writeTrap>:
800003a8: 00000f17 auipc t5,0x0
800003ac: 018f0f13 addi t5,t5,24 # 800003c0 <test19_executeTrap>
800003b0: 900110b7 lui ra,0x90011
800003b4: 01008093 addi ra,ra,16 # 90011010 <ROM_7+0x10005010>
800003b8: 00008067 ret
800003bc: 0080006f j 800003c4 <fail>
800003c0 <test19_executeTrap>:
800003c0: 0180006f j 800003d8 <pass>
800003c4 <fail>:
800003c4: 18005073 csrwi satp,0
800003c8: 0040006f j 800003cc <failFence>
800003cc <failFence>:
800003cc: f0100137 lui sp,0xf0100
800003d0: f2410113 addi sp,sp,-220 # f00fff24 <ROM_7+0x700f3f24>
800003d4: 01c12023 sw t3,0(sp)
800003d8 <pass>:
800003d8: 18005073 csrwi satp,0
800003dc: 0040006f j 800003e0 <passFence>
800003e0 <passFence>:
800003e0: f0100137 lui sp,0xf0100
800003e4: f2010113 addi sp,sp,-224 # f00fff20 <ROM_7+0x700f3f20>
800003e8: 00012023 sw zero,0(sp)
800003ec <trap>:
800003ec: fc0e8ce3 beqz t4,800003c4 <fail>
800003f0: 342020f3 csrr ra,mcause
800003f4: 341020f3 csrr ra,mepc
800003f8: 341f1073 csrw mepc,t5
800003fc: 30200073 mret
80000400: 00000013 nop
80000404: 00000013 nop
80000408: 00000013 nop
@ -10329,7 +10351,7 @@ Disassembly of section .crt_section:
8000a00a: 5b5a lw s6,180(sp)
8000a00c: 5d5c lw a5,60(a0)
8000a00e: 5f5e lw t5,244(sp)
8000a010: 00000013 nop
8000a010: 00008067 ret
8000a014: 00000013 nop
8000a018: 00000013 nop
8000a01c: 00000013 nop

162
src/test/cpp/raw/mmu/build/mmu.hex
View file

@ -1,68 +1,68 @@
:0200000480007A
:100000006F008002130000001300000013000000C6
:100010001300000013000000130000001300000094
:100020006F00801F73002030970000009380001F36
:100030007390503073905010130E100097700000A2
:10004000938040FC372126271301415283A04000B2
:100050006394201C130E2000970000009380000280
:1000600073901034B72000009380008073900030AC
:10007000730020306F00401A130E3000B7100000DC
:1000800093800080739000309700000093804001BF
:1000900073901034730020306F000018130E40006E
:1000A00097800000938000F63731363713014153B3
:1000B00083A0400063922016130E5000971000009A
:1000C00093804074172100001301C1F313512100E4
:1000D0001361110123A0200097200000938080F27B
:1000E00037010080135121001361F10123A020008A
:1000F000130E5000972000009380C080173100003D
:10010000130141F0135121001361110123A02000BC
:1001100097300000938080F117910000130181EE69
:10012000135121001361F10123A02000130E500090
:10013000972000009380008D17010000130181ECCF
:10014000135121001361F10123A02000971000003A
:10015000938040EB93D0C00037010080B3E02000D3
:1001600073900018130E6000B7A000909380800079
:1001700037514A4B1301819483A00000639E2008ED
:10018000130E7000B7A00090938000363701EEAADE
:100190001301110023A0200083A00000639E20060D
:1001A000130E800097C00020938000E637717677A9
:1001B0001301415783A0000063902006130E9000A6
:1001C000B7A000A0938000363701EEAA13012100EA
:1001D00023A0200083A0000063902004130EA00041
:1001E00073500018979000009380C0173701EEAA53
:1001F0001301110083A000006390200297A000006B
:10020000938040163701EEAA1301210083A000005D
:10021000639420006F008001735000186F0040004D
:10022000370110F0130141F22320C101735000186F
:100230006F004000370110F0130101F2232001008C
:100240001300000013000000130000001300000062
:100250001300000013000000130000001300000052
:100260001300000013000000130000001300000042
:100270001300000013000000130000001300000032
:100280001300000013000000130000001300000022
:100290001300000013000000130000001300000012
:1002A0001300000013000000130000001300000002
:1002B00013000000130000001300000013000000F2
:1002C00013000000130000001300000013000000E2
:1002D00013000000130000001300000013000000D2
:1002E00013000000130000001300000013000000C2
:1002F00013000000130000001300000013000000B2
:1003000013000000130000001300000013000000A1
:100310001300000013000000130000001300000091
:100320001300000013000000130000001300000081
:100330001300000013000000130000001300000071
:100340001300000013000000130000001300000061
:100350001300000013000000130000001300000051
:100360001300000013000000130000001300000041
:100370001300000013000000130000001300000031
:100380001300000013000000130000001300000021
:100390001300000013000000130000001300000011
:1003A0001300000013000000130000001300000001
:1003B00013000000130000001300000013000000F1
:1003C00013000000130000001300000013000000E1
:1003D00013000000130000001300000013000000D1
:1003E00013000000130000001300000013000000C1
:1003F00013000000130000001300000013000000B1
:10000000930E0000970000009380803E7390503064
:10001000130E1000977000009380C0FE3721262732
:100020001301415283A04000639E2038130E20002C
:10003000970000009380000273901034B7200000F6
:100040009380008073900030730020306F00803701
:10005000130E3000B71000009380008073900030C2
:10006000970000009380400173901034730020309B
:100070006F004035130E400097800000938080F899
:10008000373136371301415383A04000639C20323F
:10009000130E5000971000009380C07617210000C7
:1000A000130141F6135121001361110123A0200017
:1000B00097200000938000F5370100801351210044
:1000C0001361F10123A02000130E500097200000BF
:1000D00093804083173100001301C1F213512100B6
:1000E0001361110123A0200097300000938000F4D9
:1000F00017910000130101F1135121001361F10167
:1001000023A02000973000009380C0F317A10000C7
:10011000130141EF135121001361310123A020008D
:1001200097300000938040F217A10000130181ED89
:10013000135121001361710123A0200097300000AA
:100140009380C0F017A100001301C1EB13512100EF
:100150001361910123A0200097300000938040EFAD
:1001600017A10000130101EA135121001361B1012D
:1001700023A02000130E5000972000009380808859
:1001800017010000130101E8135121001361F1016F
:1001900023A02000130E500097200000938080962B
:1001A00023A00000971000009380C0E593D0C0000A
:1001B00037010080B3E0200073900018130E600038
:1001C000B7A000909380800037514A4B130181946F
:1001D00083A000006398201E130E7000B7A000904B
:1001E000938000363701EEAA1301110023A02000EE
:1001F00083A000006398201C130E800097C000208D
:10020000938080E0377176771301415783A0000017
:10021000639A201A130E9000B7A000A093800036B6
:100220003701EEAA1301210023A0200083A00000C3
:10023000639A2018130EA0007350001897900000C6
:10024000938040123701EEAA1301110083A0000031
:10025000639A2016130EB00097A0000093808010C0
:100260003701EEAA1301210083A00000639C201433
:1002700097100000938000D993D0C0003701008010
:10028000B3E0200073900018130EC000930E10000E
:10029000170F0000130F0F01730000006F00801292
:1002A000130ED000170F0000130F4F01B70000B05E
:1002B00083A080006F000011130EE000170F0000F4
:1002C000130F4F01B70000B023A410006F00800F80
:1002D000130EF000170F0000130F4F01B70000B00E
:1002E000678000006F00000E130E0001930E0000E7
:1002F000B70001909380800037615A5B13018195AC
:1003000083A000006390200CB710019093808000C0
:1003100037615A5B1301819583A000006394200A22
:10032000B73001909380800037615A5B130181954B
:1003300083A0000063982008130E1001B7100190ED
:10034000938000363701EEAA1301310023A020006C
:1003500083A0000063982006130E20019700000080
:100360009380800137210190130101016700010092
:100370006F004005930E1000170F0000130F8F0140
:10038000B72001909380000183A000006F008003DC
:10039000170F0000130F8F01B730019093800001F9
:1003A00023A010006F000002170F0000130F8F0131
:1003B000B710019093800001678000006F008000FB
:1003C0006F008001735000186F004000370110F07B
:1003D000130141F22320C101735000186F00400047
:1003E000370110F0130101F223200100E38C0EFC11
:1003F000F3202034F320103473101F3473002030A6
:1004000013000000130000001300000013000000A0
:100410001300000013000000130000001300000090
:100420001300000013000000130000001300000080
@ -2560,7 +2560,7 @@
:109FE0001300000013000000130000001300000025
:109FF0001300000013000000130000001300000015
:10A00000505152535455565758595A5B5C5D5E5FD8
:10A0100013000000130000001300000013000000F4
:10A010006780000013000000130000001300000020
:10A0200013000000130000001300000013000000E4
:10A0300013000000130000001300000013000000D4
:10A0400013000000130000001300000013000000C4
@ -3256,34 +3256,6 @@
:10CB600000000000000000000000000000000000C5
:10CB700000000000000000000000000000000000B5
:10CB800000000000000000000000000000000000A5
:10CB90000000000000000000000000000000000095
:10CBA0000000000000000000000000000000000085
:10CBB0000000000000000000000000000000000075
:10CBC0000000000000000000000000000000000065
:10CBD0000000000000000000000000000000000055
:10CBE0000000000000000000000000000000000045
:10CBF0000000000000000000000000000000000035
:10CC00000000000000000000000000000000000024
:10CC10000000000000000000000000000000000014
:10CC20000000000000000000000000000000000004
:10CC300000000000000000000000000000000000F4
:10CC400000000000000000000000000000000000E4
:10CC500000000000000000000000000000000000D4
:10CC600000000000000000000000000000000000C4
:10CC700000000000000000000000000000000000B4
:10CC800000000000000000000000000000000000A4
:10CC90000000000000000000000000000000000094
:10CCA0000000000000000000000000000000000084
:10CCB0000000000000000000000000000000000074
:10CCC0000000000000000000000000000000000064
:10CCD0000000000000000000000000000000000054
:10CCE0000000000000000000000000000000000044
:10CCF0000000000000000000000000000000000034
:10CD00000000000000000000000000000000000023
:10CD10000000000000000000000000000000000013
:10CD20000000000000000000000000000000000003
:10CD300000000000000000000000000000000000F3
:10CD400000000000000000000000000000000000E3
:08CD50000000000000000000DB
:04000005800000284F
:04CB900000000000A1
:040000058000000077
:00000001FF

147
src/test/cpp/raw/mmu/src/crt.S
View file

@ -2,24 +2,10 @@
ROM_SUPER_0:
j _start
nop
nop
nop
nop
nop
nop
nop
.global trap_entry
trap_entry:
j fail
mret
_start:
la x1, fail
li x29, 0 //Do not allow trap
la x1, trap
csrw mtvec, x1
csrw stvec, x1
test1: //test ram
li x28, 1
@ -85,6 +71,30 @@ test5: //setup MMU
ori x2, x2, 0x1F
sw x2, 0(x1)
la x1, MMU_TABLE_2 + 0x010*4 // Read Only
la x2, ROM_5
srli x2, x2, 2
ori x2, x2, 0x11 + (0x1 << 1)
sw x2, 0(x1)
la x1, MMU_TABLE_2 + 0x011*4 // Read Write
la x2, ROM_5
srli x2, x2, 2
ori x2, x2, 0x11 + (0x3 << 1)
sw x2, 0(x1)
la x1, MMU_TABLE_2 + 0x012*4 // Execute only
la x2, ROM_5
srli x2, x2, 2
ori x2, x2, 0x11 + (0x4 << 1)
sw x2, 0(x1)
la x1, MMU_TABLE_2 + 0x013*4 //Read Execute
la x2, ROM_5
srli x2, x2, 2
ori x2, x2, 0x11 + (0x5 << 1)
sw x2, 0(x1)
li x28, 5
la x1, MMU_TABLE_0 + 0xA00
la x2, ROM_SUPER_0
@ -92,6 +102,10 @@ test5: //setup MMU
ori x2, x2, 0x1F
sw x2, 0(x1)
li x28, 5
la x1, MMU_TABLE_0 + 0xB00
sw x0, 0(x1)
la x1, MMU_TABLE_0
srli x1, x1, 12
@ -147,18 +161,111 @@ test10: //check previously written value without the MMU
bne x1, x2, fail
test11:
li x28, 11
la x1, ROM_SUPER_0 + 0xA360
li x2, 0xAAEE0002
lw x1, 0(x1)
bne x1, x2, fail
la x1, MMU_TABLE_0
srli x1, x1, 12
li x2, 0x80000000
or x1, x1, x2
csrw satp, x1
test12: //Dummy trap
li x28, 12
li x29, 1 //Allow trap
la x30, test13 // trap return address
ecall
j fail
test13: //Trap load page fault
li x28, 13
la x30, test14
li x1, 0xB0000000
lw x1, 8(x1)
j fail
test14: //Trap store page fault
li x28, 14
la x30, test15
li x1, 0xB0000000
sw x1, 8(x1)
j fail
test15: //Trap instruction fetch
li x28, 15
la x30, test15_end
li x1, 0xB0000000
jr x1
j fail
test15_end:
test16: //Test limited read access
li x28, 16
li x29, 0 //disable trap
li x1, 0x90010008
li x2, 0x5B5A5958
lw x1, 0(x1)
bne x1, x2, fail
li x1, 0x90011008
li x2, 0x5B5A5958
lw x1, 0(x1)
bne x1, x2, fail
li x1, 0x90013008
li x2, 0x5B5A5958
lw x1, 0(x1)
bne x1, x2, fail
test17: //Test limited write access
li x28, 17
li x1, 0x90011360
li x2, 0xAAEE0003
sw x2, 0(x1)
lw x1, 0(x1)
bne x1, x2, fail
test18: //Test limited execute access
li x28, 18
la x1, test18_end
li x2, 0x90012010
jr x2
j fail
test18_end:
test19: //exception by access limitations
li x29, 1 //Allow trap
la x30, test19_readTrap
li x1, 0x90012010
lw x1, 0(x1)
j fail
test19_readTrap:
la x30, test19_writeTrap
li x1, 0x90013010
sw x1, 0(x1)
j fail
test19_writeTrap:
la x30, test19_executeTrap
li x1, 0x90011010
jr x1
j fail
test19_executeTrap:
j pass
@ -178,6 +285,13 @@ passFence:
sw x0, 0(x2)
trap:
beq x29, x0, fail
csrr x1, mcause
csrr x1, mepc
csrw mepc, x30
mret
nop
nop
@ -243,6 +357,7 @@ ROM_5:
.word 0x57565554
.word 0x5B5A5958
.word 0x5F5E5D5C
jr x1
.align 12
ROM_6:

8
src/test/cpp/regression/main.cpp
View file

@ -724,7 +724,7 @@ public:
pcWrite(sepc);
}break;
case 0x00000073:{ //ECALL
exception(0, 11);
exception(0, 8+privilege);
}break;
case 0x10500073:{ //WFI
pcWrite(pc + 4);
@ -1343,7 +1343,11 @@ public:
}
if(riscvRefEnable) if(rfWriteValid != riscvRef.rfWriteValid ||
(rfWriteValid && (rfWriteAddress!= riscvRef.rfWriteAddress || rfWriteData!= riscvRef.rfWriteData))){
cout << "regFile write missmatch at " << endl;
cout << "regFile write missmatch ";
if(rfWriteValid) cout << "REF: RF[" << riscvRef.rfWriteAddress << "] = 0x" << hex << riscvRef.rfWriteData << dec << " ";
if(rfWriteValid) cout << "RTL: RF[" << rfWriteAddress << "] = 0x" << hex << rfWriteData << dec << " ";
cout << endl;
fail();
}
}