Add GenFullWithOfficialRiscvDebug

This commit is contained in:
Dolu1990 2023-11-03 10:46:49 +01:00
parent 11cc9b1cf2
commit e6998d1cb3
3 changed files with 143 additions and 11 deletions

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@ -1331,6 +1331,8 @@ init
halt halt
``` ```
A full example can be found in GenFullWithOfficialRiscvDebug.scala
#### YamlPlugin #### YamlPlugin
This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required

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@ -144,19 +144,19 @@ object TestsWorkspace {
withDouble = true, withDouble = true,
externalFpu = false, externalFpu = false,
simHalt = true, simHalt = true,
privilegedDebug = false privilegedDebug = true
) )
// config.plugins += new EmbeddedRiscvJtag( config.plugins += new EmbeddedRiscvJtag(
// p = DebugTransportModuleParameter( p = DebugTransportModuleParameter(
// addressWidth = 7, addressWidth = 7,
// version = 1, version = 1,
// idle = 7 idle = 7
// ), ),
// debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")), debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
// withTunneling = false, withTunneling = false,
// withTap = true withTap = true
// ) )
// l.foreach{ // l.foreach{
// case p : EmbeddedRiscvJtag => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset"))) // case p : EmbeddedRiscvJtag => p.debugCd.load(ClockDomain.current.copy(reset = Bool().setName("debug_reset")))

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@ -0,0 +1,130 @@
package vexriscv.demo
import spinal.core._
import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
import vexriscv.plugin._
import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
/**
* This an example of VexRiscv configuration which can run the official RISC-V debug.
* You can for instance :
* - generate this VexRiscv
* - cd src/test/cpp/regression
* - make IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes SUPERVISOR=yes CSR=yes RVF=yes RVD=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes
*
* This will run a simulation of the CPU which wait for a tcp-jtag connection from openocd.
* That con connection can be done via openocd :
* - src/openocd -f config.tcl
*
* Were config.tcl is the following :
*
* ##############################################
* interface jtag_tcp
* adapter speed 5000
*
* set _CHIPNAME riscv
* jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10002FFF
*
* set _TARGETNAME $_CHIPNAME.cpu
*
* target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
*
* init
* halt
*
* echo "Ready for Remote Connections"
* ##############################################
*/
object GenFullWithOfficialRiscvDebug extends App{
def config = VexRiscvConfig(
plugins = List(
new IBusCachedPlugin(
prediction = DYNAMIC,
config = InstructionCacheConfig(
cacheSize = 4096,
bytePerLine =32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchIllegalAccess = true,
catchAccessFault = true,
asyncTagMemory = false,
twoCycleRam = true,
twoCycleCache = true
),
memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 4
)
),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
cpuDataWidth = 32,
memDataWidth = 32,
catchAccessError = true,
catchIllegal = true,
catchUnaligned = true
),
memoryTranslatorPortConfig = MmuPortConfig(
portTlbSize = 6
)
),
new MmuPlugin(
virtualRange = _(31 downto 28) === 0xC,
ioRange = _(31 downto 28) === 0xF
),
new DecoderSimplePlugin(
catchIllegalInstruction = true
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
),
new IntAluPlugin,
new SrcPlugin(
separatedAddSub = false,
executeInsertion = true
),
new FullBarrelShifterPlugin,
new HazardSimplePlugin(
bypassExecute = true,
bypassMemory = true,
bypassWriteBack = true,
bypassWriteBackBuffer = true,
pessimisticUseSrc = false,
pessimisticWriteRegFile = false,
pessimisticAddressMatch = false
),
new MulPlugin,
new DivPlugin,
new CsrPlugin(CsrPluginConfig.small(0x80000020l).copy(withPrivilegedDebug = true)),
new EmbeddedRiscvJtag(
p = DebugTransportModuleParameter(
addressWidth = 7,
version = 1,
idle = 7
),
debugCd = ClockDomain.current.copy(reset = Bool().setName("debugReset")),
withTunneling = false,
withTap = true
),
new BranchPlugin(
earlyBranch = false,
catchAddressMisaligned = true
),
new YamlPlugin("cpu0.yaml")
)
)
def cpu() = new VexRiscv(config){
println(config.getRegressionArgs().mkString(" "))
}
SpinalVerilog(cpu())
}