Add D$ single line flush support
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@ -1038,6 +1038,8 @@ There is at least one cycle latency between a cmd and the corresponding rsp. The
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Multi way cache implementation with writh-through and allocate on read strategy. (Documentation is WIP)
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You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range of one line via the instruction 0x500F | RS1 << 15 where RS1 should not be X0.
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#### MulPlugin
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Implements the multiplication instruction from the RISC-V M extension. Its implementation was done in a FPGA friendly way by using 4 17*17 bit multiplications.
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@ -40,6 +40,7 @@ case class DataCacheConfig(cacheSize : Int,
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assert(isPow2(pendingMax))
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assert(rfDataWidth <= memDataWidth)
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def lineCount = cacheSize/bytePerLine/wayCount
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def sizeMax = log2Up(bytePerLine)
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def sizeWidth = log2Up(sizeMax + 1)
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val aggregationWidth = if(withWriteAggregation) log2Up(memDataBytes+1) else 0
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@ -193,13 +194,18 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
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}
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}
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case class DataCacheFlush(lineCount : Int) extends Bundle{
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val singleLine = Bool()
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val lineId = UInt(log2Up(lineCount) bits)
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}
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case class DataCacheCpuBus(p : DataCacheConfig, mmu : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
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val execute = DataCacheCpuExecute(p)
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val memory = DataCacheCpuMemory(p, mmu)
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val writeBack = DataCacheCpuWriteBack(p)
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val redo = Bool()
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val flush = Event
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val flush = Stream(DataCacheFlush(p.lineCount))
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override def asMaster(): Unit = {
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master(execute)
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@ -849,6 +855,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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io.cpu.execute.haltIt := True
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when(!hold) {
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counter := counter + 1
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when(io.cpu.flush.singleLine){
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counter.msb := True
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}
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}
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}
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@ -860,6 +869,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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when(start){
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waitDone := True
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counter := 0
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when(io.cpu.flush.singleLine){
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counter := U"0" @@ io.cpu.flush.lineId
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}
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}
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}
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@ -228,7 +228,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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decoderService.addDefault(MEMORY_MANAGMENT, False)
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decoderService.add(MANAGEMENT, List(
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MEMORY_MANAGMENT -> True
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MEMORY_MANAGMENT -> True,
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RS1_USE -> True
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))
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withWriteResponse match {
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@ -343,6 +344,8 @@ class DBusCachedPlugin(val config : DataCacheConfig,
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}
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cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)
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cache.io.cpu.flush.singleLine := input(INSTRUCTION)(Riscv.rs1Range) =/= 0
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cache.io.cpu.flush.lineId := U(input(RS1) >> log2Up(bytePerLine)).resized
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cache.io.cpu.execute.args.totalyConsistent := input(MEMORY_FORCE_CONSTISTENCY)
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arbitration.haltItself setWhen(cache.io.cpu.flush.isStall || cache.io.cpu.execute.haltIt)
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