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Same thing for DBusSimpleBus.

This commit is contained in:
Tom Verbeure 2019-03-23 23:36:13 +00:00
parent 1afad4f240
commit ea62fd0e16
1 changed files with 8 additions and 1 deletions
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9
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -63,6 +63,12 @@ object DBusSimpleBus{
useBTE = true,
useCTI = true
)
def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig(
addressWidth = 32,
dataWidth = 32
)
}
case class DBusSimpleBus() extends Bundle with IMasterSlave{
@ -178,7 +184,8 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{
}
def toPipelinedMemoryBus() : PipelinedMemoryBus = {
val bus = PipelinedMemoryBus(32,32)
val pipelinedMemoryBusConfig = DBusSimpleBus.getPipelinedMemoryBusConfig()
val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig)
bus.cmd.valid := cmd.valid
bus.cmd.write := cmd.wr
bus.cmd.address := cmd.address.resized