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MuraxSim 1.0.0

This commit is contained in:
Dolu1990 2017-12-17 17:57:09 +01:00
parent dda5372a6c
commit ebda7526b5
6 changed files with 121 additions and 81 deletions
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2
.gitignore vendored
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@ -42,3 +42,5 @@ obj_dir
*.tcl
*.o
*verilatorSim/

1
src/main/scala/vexriscv/demo/Murax.scala
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@ -127,6 +127,7 @@ object MuraxConfig{
bypassWriteBack = true,
bypassWriteBackBuffer = true
)
// config.cpuPlugins(config.cpuPlugins.indexWhere(_.isInstanceOf[LightShifterPlugin])) = new FullBarrielShifterPlugin()
config
}

99
src/test/scala/vexriscv/MuraxSim.scala
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@ -1,24 +1,21 @@
package vexriscv
import java.awt.Graphics
import java.io.{InputStream, OutputStream}
import java.net.ServerSocket
import javax.swing.{JFrame, JPanel}
import spinal.sim._
import spinal.core._
import spinal.core.SimManagedApi._
import vexriscv.demo.{Murax, MuraxConfig}
import scala.concurrent.Future
import scala.util.Random
import scala.concurrent.ExecutionContext.Implicits.global
import java.awt.Graphics
import javax.swing.{JFrame, JPanel}
object MuraxSim {
def main(args: Array[String]): Unit = {
// val config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
val config = MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
SimConfig(new Murax(config)).doManagedSim{dut =>
SimConfig(new Murax(config)).allOptimisation.doManagedSim{dut =>
val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
val jtagClkPeriod = mainClkPeriod*4
val uartBaudRate = 115200
@ -41,87 +38,27 @@ object MuraxSim {
cycleCounter += 1
if(cycleCounter == 100000){
val currentTime = System.nanoTime()
// println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
println(f"${cycleCounter/((currentTime - lastTime)*1e-9)*1e-3}%4.0f kHz")
lastTime = currentTime
cycleCounter = 0
}
}
}
val tcpJtag = TcpJtag(
jtag = dut.io.jtag,
jtagClkPeriod = jtagClkPeriod
)
val jtag = fork {
var inputStream : InputStream = null
var outputStream : OutputStream = null
val uartTx = UartDecoder(
uartPin = dut.io.uart.txd,
baudPeriod = uartBaudPeriod
)
val server = Future {
val socket = new ServerSocket(7894)
println("WAITING FOR TCP JTAG CONNECTION")
while (true) {
val connection = socket.accept()
connection.setTcpNoDelay(true)
outputStream = connection.getOutputStream()
inputStream = connection.getInputStream()
println("TCP JTAG CONNECTION")
}
}
while(true) {
sleep(mainClkPeriod * 1000)
while(inputStream != null && inputStream.available() != 0){
val buffer = inputStream.read()
dut.io.jtag.tms #= (buffer & 1) != 0;
dut.io.jtag.tdi #= (buffer & 2) != 0;
dut.io.jtag.tck #= (buffer & 8) != 0;
if((buffer & 4) != 0){
outputStream.write(if(dut.io.jtag.tdo.toBoolean) 1 else 0)
}
sleep(jtagClkPeriod/2)
}
}
}
val uartTx = fork{
waitUntil(dut.io.uart.txd.toBoolean == true)
while(true) {
waitUntil(dut.io.uart.txd.toBoolean == false)
sleep(uartBaudPeriod/2)
assert(dut.io.uart.txd.toBoolean == false)
sleep(uartBaudPeriod)
var buffer = 0
(0 to 7).foreachSim{ bitId =>
if(dut.io.uart.txd.toBoolean)
buffer |= 1 << bitId
sleep(uartBaudPeriod)
}
assert(dut.io.uart.txd.toBoolean == true)
print(buffer.toChar)
}
}
val uartRx = fork{
dut.io.uart.rxd #= true
while(true) {
if(System.in.available() != 0){
val buffer = System.in.read()
dut.io.uart.rxd #= false
sleep(uartBaudPeriod)
(0 to 7).foreachSim{ bitId =>
dut.io.uart.rxd #= ((buffer >> bitId) & 1) != 0
sleep(uartBaudPeriod)
}
dut.io.uart.rxd #= true
sleep(uartBaudPeriod)
} else {
sleep(uartBaudPeriod * 10)
}
}
}
val uartRx = UartEncoder(
uartPin = dut.io.uart.rxd,
baudPeriod = uartBaudPeriod
)
val leds = fork{

43
src/test/scala/vexriscv/TcpJtag.scala Normal file
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@ -0,0 +1,43 @@
package vexriscv
import java.io.{InputStream, OutputStream}
import java.net.ServerSocket
import spinal.core.SimManagedApi._
import spinal.lib.com.jtag.Jtag
import scala.concurrent.Future
import scala.concurrent.ExecutionContext.Implicits.global
object TcpJtag {
def apply(jtag: Jtag, jtagClkPeriod: Long) = fork {
var inputStream: InputStream = null
var outputStream: OutputStream = null
val server = Future {
val socket = new ServerSocket(7894)
println("WAITING FOR TCP JTAG CONNECTION")
while (true) {
val connection = socket.accept()
connection.setTcpNoDelay(true)
outputStream = connection.getOutputStream()
inputStream = connection.getInputStream()
println("TCP JTAG CONNECTION")
}
}
while (true) {
sleep(jtagClkPeriod * 200)
while (inputStream != null && inputStream.available() != 0) {
val buffer = inputStream.read()
jtag.tms #= (buffer & 1) != 0;
jtag.tdi #= (buffer & 2) != 0;
jtag.tck #= (buffer & 8) != 0;
if ((buffer & 4) != 0) {
outputStream.write(if (jtag.tdo.toBoolean) 1 else 0)
}
sleep(jtagClkPeriod / 2)
}
}
}
}

29
src/test/scala/vexriscv/UartDecoder.scala Normal file
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@ -0,0 +1,29 @@
package vexriscv
import spinal.sim._
import spinal.core.SimManagedApi._
import spinal.core.{Bool, assert}
object UartDecoder {
def apply(uartPin : Bool, baudPeriod : Long) = fork{
waitUntil(uartPin.toBoolean == true)
while(true) {
waitUntil(uartPin.toBoolean == false)
sleep(baudPeriod/2)
assert(uartPin.toBoolean == false)
sleep(baudPeriod)
var buffer = 0
(0 to 7).suspendable.foreach{ bitId =>
if(uartPin.toBoolean)
buffer |= 1 << bitId
sleep(baudPeriod)
}
assert(uartPin.toBoolean == true)
print(buffer.toChar)
}
}
}

28
src/test/scala/vexriscv/UartEncoder.scala Normal file
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@ -0,0 +1,28 @@
package vexriscv
import spinal.sim._
import spinal.core.Bool
import spinal.core.SimManagedApi._
object UartEncoder {
def apply(uartPin : Bool, baudPeriod : Long) = fork{
uartPin #= true
while(true) {
if(System.in.available() != 0){
val buffer = System.in.read()
uartPin #= false
sleep(baudPeriod)
(0 to 7).suspendable.foreach{ bitId =>
uartPin #= ((buffer >> bitId) & 1) != 0
sleep(baudPeriod)
}
uartPin #= true
sleep(baudPeriod)
} else {
sleep(baudPeriod * 10)
}
}
}
}