Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

VexRiscvBmbGenrator now use relaxedReset

This commit is contained in:
Dolu1990 2023-03-24 08:39:07 +01:00
parent c69852c0cc
commit eeb65ed1c0
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
View File

@ -47,7 +47,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableJtag(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ def enableJtag(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG) withDebug.load(DEBUG_JTAG)
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
@ -55,7 +55,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableJtagInstructionCtrl(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ def enableJtagInstructionCtrl(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_JTAG_CTRL) withDebug.load(DEBUG_JTAG_CTRL)
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
@ -63,7 +63,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
def enableDebugBus(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{ def enableDebugBus(debugCd : ClockDomainResetGeneratorIf, resetCd : ClockDomainResetGeneratorIf) : Unit = debugCd.rework{
this.debugClockDomain.load(debugCd.outputClockDomain) this.debugClockDomain.load(debugCd.outputClockDomain)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_BUS) withDebug.load(DEBUG_BUS)
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)
@ -87,7 +87,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
val debugBmbAccessRequirements = Handle[BmbAccessParameter] val debugBmbAccessRequirements = Handle[BmbAccessParameter]
def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{ def enableDebugBmb(debugCd : Handle[ClockDomain], resetCd : ClockDomainResetGeneratorIf, mapping : AddressMapping)(implicit debugMaster : BmbImplicitDebugDecoder = null) : Unit = debugCd.on{
this.debugClockDomain.load(debugCd) this.debugClockDomain.load(debugCd)
val resetBridge = resetCd.asyncReset(debugReset, ResetSensitivity.HIGH) val resetBridge = resetCd.relaxedReset(debugReset, ResetSensitivity.HIGH)
debugAskReset.loadNothing() debugAskReset.loadNothing()
withDebug.load(DEBUG_BMB) withDebug.load(DEBUG_BMB)
if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false) if(!withRiscvDebug.isLoaded) withRiscvDebug.load(false)