IBusCachedPlugin now support memory data width multiple of 32
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Dolu1990
parent
23b8c40cab
commit
eee9927baf
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@ -70,7 +70,7 @@ case class InstructionCacheConfig( cacheSize : Int,
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def getBmbParameter() = BmbParameter(
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addressWidth = 32,
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dataWidth = 32,
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dataWidth = memDataWidth,
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lengthWidth = log2Up(this.bytePerLine),
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sourceWidth = 0,
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contextWidth = 0,
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@ -278,7 +278,6 @@ case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{
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class InstructionCache(p : InstructionCacheConfig) extends Component{
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import p._
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assert(cpuDataWidth == memDataWidth, "Need testing")
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val io = new Bundle{
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val flush = in Bool()
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val cpu = slave(InstructionCacheCpuBus(p))
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@ -287,7 +286,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val lineWidth = bytePerLine*8
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val lineCount = cacheSize/bytePerLine
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val wordWidth = Math.max(memDataWidth,32)
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val wordWidth = cpuDataWidth
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val wordWidthLog2 = log2Up(wordWidth)
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val wordPerLine = lineWidth/wordWidth
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val memWordPerLine = lineWidth/memDataWidth
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@ -295,7 +294,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val bytePerMemWord = memDataWidth/8
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val wayLineCount = lineCount/wayCount
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val wayLineLog2 = log2Up(wayLineCount)
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val wayWordCount = wayLineCount * wordPerLine
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val wayMemWordCount = wayLineCount * memWordPerLine
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val tagRange = addressWidth-1 downto log2Up(wayLineCount*bytePerLine)
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val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
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@ -314,7 +313,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
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val ways = Seq.fill(wayCount)(new Area{
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val tags = Mem(LineTag(),wayLineCount)
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val datas = Mem(Bits(memDataWidth bits),wayWordCount)
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val datas = Mem(Bits(memDataWidth bits),wayMemWordCount)
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if(preResetFlush){
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tags.initBigInt(List.fill(wayLineCount)(BigInt(0)))
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@ -2026,10 +2026,15 @@ public:
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ws->fail();
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}
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#endif
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ws->iBusAccess(address,&top->iBus_rsp_payload_data,&error);
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error = false;
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for(int idx = 0;idx < IBUS_DATA_WIDTH/32;idx++){
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bool localError;
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ws->iBusAccess(address+idx*4,((uint32_t*)&top->iBus_rsp_payload_data)+idx,&localError);
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error |= localError;
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}
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top->iBus_rsp_payload_error = error;
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pendingCount--;
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address = address + 4;
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pendingCount-=IBUS_DATA_WIDTH/32;
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address = address + IBUS_DATA_WIDTH/8;
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top->iBus_rsp_valid = 1;
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}
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if(ws->iStall) top->iBus_cmd_ready = VL_RANDOM_I(7) < 100 && pendingCount == 0;
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@ -3,6 +3,7 @@ REGRESSION_PATH?=./
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VEXRISCV_FILE?=../../../../VexRiscv.v
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IBUS?=CACHED
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IBUS_TC?=no
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IBUS_DATA_WIDTH?=32
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DBUS?=CACHED
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TRACE?=no
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TRACE_ACCESS?=no
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@ -41,8 +42,11 @@ STOP_ON_ERROR?=no
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COREMARK=no
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WITH_USER_IO?=no
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ADDCFLAGS += -CFLAGS -DREGRESSION_PATH='\"$(REGRESSION_PATH)/\"'
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ADDCFLAGS += -CFLAGS -DIBUS_${IBUS}
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ADDCFLAGS += -CFLAGS -DIBUS_DATA_WIDTH=${IBUS_DATA_WIDTH}
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ADDCFLAGS += -CFLAGS -DDBUS_${DBUS}
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ADDCFLAGS += -CFLAGS -DREDO=${REDO}
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ADDCFLAGS += -CFLAGS -pthread
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@ -354,7 +354,8 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
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val prediction = random(r, List(NONE, STATIC, DYNAMIC, DYNAMIC_TARGET))
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val relaxedPcCalculation, twoCycleCache, injectorStage = r.nextBoolean()
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val twoCycleRam = r.nextBoolean() && twoCycleCache
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val bytePerLine = List(8,16,32,64)(r.nextInt(4))
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val memDataWidth = List(32,64,128)(r.nextInt(3))
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val bytePerLine = Math.max(memDataWidth/8, List(8,16,32,64)(r.nextInt(4)))
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var cacheSize = 0
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var wayCount = 0
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do{
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@ -362,8 +363,8 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
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wayCount = 1 << r.nextInt(3)
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}while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
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new VexRiscvPosition("Cached" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{
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override def testParam = "IBUS=CACHED" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "")
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new VexRiscvPosition(s"Cached${memDataWidth}d" + (if(twoCycleCache) "2cc" else "") + (if(injectorStage) "Injstage" else "") + (if(twoCycleRam) "2cr" else "") + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(relaxedPcCalculation) "Relax" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")+ (if(tighlyCoupled)"Tc" else "")) with InstructionAnticipatedPosition{
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override def testParam = s"IBUS=CACHED IBUS_DATA_WIDTH=$memDataWidth" + (if(compressed) " COMPRESSED=yes" else "") + (if(tighlyCoupled)" IBUS_TC=yes" else "")
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override def applyOn(config: VexRiscvConfig): Unit = {
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val p = new IBusCachedPlugin(
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resetVector = 0x80000000l,
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@ -378,7 +379,7 @@ class IBusDimension(rvcRate : Double) extends VexRiscvDimension("IBus") {
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wayCount = wayCount,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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memDataWidth = memDataWidth,
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catchIllegalAccess = catchAll,
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catchAccessFault = catchAll,
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asyncTagMemory = false,
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