Add console TX in the Murax verilator
This commit is contained in:
Charles Papon
parent
fded0e7947
commit
f44b345132
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@ -12,7 +12,7 @@ public:
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schedule(uartTimeRate);
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}
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enum State {START, DATA, STOP,START_SUCCESS};
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enum State {START, DATA, STOP};
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State state = START;
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char data;
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uint32_t counter;
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@ -51,61 +51,76 @@ public:
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}
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};
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#include<pthread.h>
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#include <mutex>
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#include <queue>
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/*
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class UartRx : public SensitiveProcess{
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class UartTx : public TimeProcess{
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public:
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CData *rx;
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CData *tx;
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uint32_t uartTimeRate;
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UartRx(CData *rx, uint32_t uartTimeRate){
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this->rx = rx;
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this->uartTimeRate = uartTimeRate;
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}
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enum State {START, DATA, STOP,START_SUCCESS};
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enum State {START, DATA, STOP};
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State state = START;
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uint64_t holdTime = 0;
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CData holdValue;
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char data;
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uint32_t counter;
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virtual void tick(uint64_t time){
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if(time < holdTime){
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if(*rx != holdValue && time + (uartTimeRate>>7) < holdTime){
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cout << "UART RX FRAME ERROR at " << time << endl;
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holdTime = time;
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state = START;
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pthread_t inputThreadId;
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queue<uint8_t> inputsQueue;
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mutex inputsMutex;
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UartTx(CData *tx, uint32_t uartTimeRate){
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this->tx = tx;
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this->uartTimeRate = uartTimeRate;
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schedule(uartTimeRate);
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pthread_create(&inputThreadId, NULL, &inputThreadWrapper, this);
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*tx = 1;
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}
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}else{
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static void* inputThreadWrapper(void *uartTx){
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((UartTx*)uartTx)->inputThread();
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return NULL;
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}
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void inputThread(){
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while(1){
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uint8_t c = getchar();
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inputsMutex.lock();
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inputsQueue.push(c);
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inputsMutex.unlock();
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}
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}
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virtual void tick(){
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switch(state){
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case START:
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case START_SUCCESS:
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if(state == START_SUCCESS){
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cout << data << flush;
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state = START;
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}
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if(*rx == 0 && time > uartTimeRate){
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holdTime = time + uartTimeRate;
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holdValue = *rx;
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inputsMutex.lock();
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if(!inputsQueue.empty()){
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data = inputsQueue.front();
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inputsQueue.pop();
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inputsMutex.unlock();
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state = DATA;
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counter = 0;
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data = 0;
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*tx = 0;
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schedule(uartTimeRate);
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} else {
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inputsMutex.unlock();
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schedule(uartTimeRate*50);
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}
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break;
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case DATA:
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data |= (*rx) << counter++;
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*tx = (data >> counter) & 1;
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counter++;
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if(counter == 8){
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state = STOP;
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}
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holdValue = *rx;
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holdTime = time + uartTimeRate;
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schedule(uartTimeRate);
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break;
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case STOP:
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holdTime = time + uartTimeRate;
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holdValue = 1;
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state = START_SUCCESS;
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*tx = 1;
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schedule(uartTimeRate);
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state = START;
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break;
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}
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}
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}
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};*/
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};
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@ -13,10 +13,12 @@ public:
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ClockDomain *mainClk = new ClockDomain(&top->io_mainClk,NULL,83333,300000);
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AsyncReset *asyncReset = new AsyncReset(&top->io_asyncReset,50000);
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UartRx *uartRx = new UartRx(&top->io_uart_txd,1.0e12/115200);
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UartTx *uartTx = new UartTx(&top->io_uart_rxd,1.0e12/115200);
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timeProcesses.push_back(mainClk);
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timeProcesses.push_back(asyncReset);
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timeProcesses.push_back(uartRx);
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timeProcesses.push_back(uartTx);
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Jtag *jtag = new Jtag(&top->io_jtag_tms,&top->io_jtag_tdi,&top->io_jtag_tdo,&top->io_jtag_tck,83333*4);
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timeProcesses.push_back(jtag);
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@ -2,7 +2,7 @@ DEBUG?=no
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TRACE?=no
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PRINT_PERF?=no
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TRACE_START=0
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ADDCFLAGS += -CFLAGS -pthread
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ADDCFLAGS += -CFLAGS -pthread -LDFLAGS -pthread
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ifeq ($(TRACE),yes)
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@ -1,88 +1,51 @@
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[*]
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[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
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[*] Sat Jul 29 10:39:29 2017
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[*] Mon Jul 31 17:03:11 2017
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[*]
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/Murax.vcd"
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[dumpfile_mtime] "Sat Jul 29 10:39:12 2017"
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[dumpfile_size] 230220943
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[dumpfile_mtime] "Mon Jul 31 17:03:01 2017"
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[dumpfile_size] 1539276802
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[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/murax/murax.gtkw"
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[timestart] 56764536000
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[timestart] 300964770000
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[size] 1776 953
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[pos] -775 -353
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*-19.000000 56765697000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[pos] -1 -353
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*-23.000000 300989600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.Murax.
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[sst_width] 269
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[signals_width] 488
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[treeopen] TOP.Murax.system_uartCtrl.
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[treeopen] TOP.Murax.system_uartCtrl.uartCtrl_1.
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[sst_width] 454
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[signals_width] 327
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[sst_expanded] 1
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[sst_vpaned_height] 503
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@22
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TOP.io_gpioA_read[31:0]
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TOP.io_gpioA_writeEnable[31:0]
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TOP.io_gpioA_write[31:0]
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[color] 3
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TOP.Murax.system_mainBus_cmd_payload_address[31:0]
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[color] 3
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TOP.Murax.system_mainBus_cmd_payload_data[31:0]
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[color] 3
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TOP.Murax.system_mainBus_cmd_payload_mask[3:0]
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[sst_vpaned_height] 279
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@28
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[color] 3
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TOP.Murax.system_mainBus_cmd_valid
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[color] 3
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TOP.Murax.system_mainBus_cmd_ready
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[color] 3
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TOP.Murax.system_mainBus_cmd_payload_wr
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TOP.Murax.system_uartCtrl.io_uart_rxd
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TOP.Murax.system_uartCtrl.io_uart_txd
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TOP.Murax.system_uartCtrl.io_interrupt
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TOP.Murax.system_cpu.CsrPlugin_mstatus_MIE
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@22
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[color] 3
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TOP.Murax.system_mainBus_rsp_payload_data[31:0]
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TOP.Murax.system_uartCtrl.streamFifo_2.io_push_payload[7:0]
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@28
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[color] 3
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TOP.Murax.system_mainBus_rsp_valid
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TOP.Murax.system_ram_bus_cmd_valid
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TOP.Murax.system_ram_bus_cmd_ready
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TOP.Murax.system_uartCtrl.streamFifo_2.io_push_valid
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TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_valid
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TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_ready
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@22
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TOP.Murax.system_ram_bus_cmd_payload_address[31:0]
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TOP.Murax.system_ram_bus_cmd_payload_data[31:0]
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TOP.Murax.system_ram_bus_cmd_payload_mask[3:0]
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TOP.Murax.system_uartCtrl.streamFifo_2.io_pop_payload[7:0]
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_read_payload[7:0]
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@28
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TOP.Murax.system_ram_bus_cmd_payload_wr
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_read_valid
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.stateMachine_state[2:0]
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@22
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TOP.Murax.system_ram_bus_rsp_payload_data[31:0]
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.stateMachine_shifter[7:0]
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@28
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TOP.Murax.system_ram_bus_rsp_valid
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@22
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[color] 1
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TOP.Murax.system_apbBridge_apb_PADDR[19:0]
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@28
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TOP.Murax.system_apbBridge_apb_PSEL[0]
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TOP.Murax.system_apbBridge_apb_PENABLE
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@22
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TOP.Murax.system_apbBridge_apb_PRDATA[31:0]
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@28
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TOP.Murax.system_apbBridge_apb_PREADY
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@22
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TOP.Murax.system_apbBridge_apb_PWDATA[31:0]
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@28
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TOP.Murax.system_apbBridge_apb_PWRITE
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TOP.Murax.system_cpu.DebugPlugin_haltIt
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TOP.Murax.system_cpu.DebugPlugin_haltIt
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TOP.Murax.system_cpu.decode_arbitration_haltIt
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TOP.Murax.system_cpu.execute_arbitration_haltItByOther
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TOP.Murax.system_cpu.fetch_arbitration_haltIt
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TOP.Murax.system_cpu.memory_arbitration_haltIt
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TOP.Murax.system_cpu.prefetch_arbitration_haltIt
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TOP.Murax.system_cpu.writeBack_arbitration_haltIt
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TOP.Murax.system_cpu.prefetch_IBusSimplePlugin_pendingCmd
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@22
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TOP.Murax.system_cpu.iBus_cmd_payload_pc[31:0]
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@28
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TOP.Murax.system_cpu.iBus_cmd_ready
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.bitTimer_tick
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.bitTimer_counter[2:0]
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@29
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TOP.Murax.system_cpu.iBus_cmd_valid
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@22
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TOP.Murax.system_cpu.iBus_rsp_inst[31:0]
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.io_rxd
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@28
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TOP.Murax.system_cpu.iBus_rsp_ready
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_value
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_tick
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_samples_1
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TOP.Murax.system_uartCtrl.uartCtrl_1.rx.sampler_samples_2
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[pattern_trace] 1
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[pattern_trace] 0
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