DataCache.withInternalLrSc reserved clearing fix
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@ -864,8 +864,8 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
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val lrSc = withInternalLrSc generate new Area{
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val reserved = RegInit(False)
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when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc){
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reserved := !request.wr
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when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){
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reserved := False
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}
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}
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