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VexRiscv
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Remove rv64 opcode (shift and lwu) 

Thanks Milan
This commit is contained in:
Dolu1990 2022-10-27 15:44:50 +02:00
parent d70794f252
commit f71234786f
3 changed files with 8 additions and 9 deletions
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7
src/main/scala/vexriscv/Riscv.scala
View File

@ -45,12 +45,12 @@ object Riscv{
def AND = M"0000000----------111-----0110011" def AND = M"0000000----------111-----0110011"
def ADDI = M"-----------------000-----0010011" def ADDI = M"-----------------000-----0010011"
def SLLI = M"000000-----------001-----0010011" def SLLI = M"0000000----------001-----0010011"
def SLTI = M"-----------------010-----0010011" def SLTI = M"-----------------010-----0010011"
def SLTIU = M"-----------------011-----0010011" def SLTIU = M"-----------------011-----0010011"
def XORI = M"-----------------100-----0010011" def XORI = M"-----------------100-----0010011"
def SRLI = M"000000-----------101-----0010011" def SRLI = M"0000000----------101-----0010011"
def SRAI = M"010000-----------101-----0010011" def SRAI = M"0100000----------101-----0010011"
def ORI = M"-----------------110-----0010011" def ORI = M"-----------------110-----0010011"
def ANDI = M"-----------------111-----0010011" def ANDI = M"-----------------111-----0010011"
@ -59,7 +59,6 @@ object Riscv{
def LW = M"-----------------010-----0000011" def LW = M"-----------------010-----0000011"
def LBU = M"-----------------100-----0000011" def LBU = M"-----------------100-----0000011"
def LHU = M"-----------------101-----0000011" def LHU = M"-----------------101-----0000011"
def LWU = M"-----------------110-----0000011"
def SB = M"-----------------000-----0100011" def SB = M"-----------------000-----0100011"
def SH = M"-----------------001-----0100011" def SH = M"-----------------001-----0100011"
def SW = M"-----------------010-----0100011" def SW = M"-----------------010-----0100011"

6
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -171,12 +171,12 @@ class DBusCachedPlugin(val config : DataCacheConfig,
decoderService.addDefault(MEMORY_ENABLE, False) decoderService.addDefault(MEMORY_ENABLE, False)
decoderService.add( decoderService.add(
List(LB, LH, LW, LBU, LHU, LWU).map(_ -> loadActions) ++ List(LB, LH, LW, LBU, LHU).map(_ -> loadActions) ++
List(SB, SH, SW).map(_ -> storeActions) List(SB, SH, SW).map(_ -> storeActions)
) )
if(withLrSc){ if(withLrSc){
List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e => List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
decoderService.add(e, Seq(MEMORY_LRSC -> False)) decoderService.add(e, Seq(MEMORY_LRSC -> False))
) )
decoderService.add( decoderService.add(
@ -199,7 +199,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
} }
if(withAmo){ if(withAmo){
List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e => List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
decoderService.add(e, Seq(MEMORY_AMO -> False)) decoderService.add(e, Seq(MEMORY_AMO -> False))
) )
val amoActions = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq( val amoActions = storeActions.filter(_._1 != SRC2_CTRL) ++ Seq(

4
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
View File

@ -340,13 +340,13 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
decoderService.addDefault(MEMORY_ENABLE, False) decoderService.addDefault(MEMORY_ENABLE, False)
decoderService.add( decoderService.add(
(if(onlyLoadWords) List(LW) else List(LB, LH, LW, LBU, LHU, LWU)).map(_ -> loadActions) ++ (if(onlyLoadWords) List(LW) else List(LB, LH, LW, LBU, LHU)).map(_ -> loadActions) ++
List(SB, SH, SW).map(_ -> storeActions) List(SB, SH, SW).map(_ -> storeActions)
) )
if(withLrSc){ if(withLrSc){
List(LB, LH, LW, LBU, LHU, LWU, SB, SH, SW).foreach(e => List(LB, LH, LW, LBU, LHU, SB, SH, SW).foreach(e =>
decoderService.add(e, Seq(MEMORY_ATOMIC -> False)) decoderService.add(e, Seq(MEMORY_ATOMIC -> False))
) )
decoderService.add( decoderService.add(