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Add SMP synthesis

This commit is contained in:
Dolu1990 2020-04-10 14:27:39 +02:00
parent 296cb44bc4
commit f71f360e32
2 changed files with 12 additions and 3 deletions
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4
src/main/scala/vexriscv/demo/Linux.scala
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@ -134,7 +134,7 @@ make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISO
object LinuxGen {
def configFull(litex : Boolean, withMmu : Boolean) = {
def configFull(litex : Boolean, withMmu : Boolean, withSmp : Boolean = false) = {
val config = VexRiscvConfig(
plugins = List(
//Uncomment the whole IBusSimplePlugin and comment IBusCachedPlugin if you want uncached iBus config
@ -201,6 +201,8 @@ object LinuxGen {
catchAccessError = true,
catchIllegal = true,
catchUnaligned = true,
withExclusive = withSmp,
withInvalidate = withSmp,
withLrSc = true,
withAmo = true
// )

11
src/main/scala/vexriscv/demo/SynthesisBench.scala
View File

@ -146,8 +146,15 @@ object VexRiscvSynthesisBench {
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true))).setDefinitionName(getRtlPath().split("\\.").head))
}
val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced)
// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll)
val linuxBalancedSmp = new Rtl {
override def getName(): String = "VexRiscv linux balanced SMP"
override def getRtlPath(): String = "VexRiscvLinuxBalancedSmp.v"
SpinalConfig(inlineRom = true).generateVerilog(wrap(new VexRiscv(LinuxGen.configFull(false, true, withSmp = true))).setDefinitionName(getRtlPath().split("\\.").head))
}
// val rtls = List(twoStage, twoStageBarell, twoStageMulDiv, twoStageAll, smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full, linuxBalanced, linuxBalancedSmp)
val rtls = List(linuxBalanced, linuxBalancedSmp)
// val rtls = List(smallest)
val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) ++ List(
new Target {