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VexRiscv
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This commit is contained in:
Dolu1990 2018-10-12 17:13:54 +02:00
parent 2b29690010
commit f903df4b66
3 changed files with 16 additions and 17 deletions
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2
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -38,7 +38,7 @@ object TestsWorkspace {
prediction = STATIC, prediction = STATIC,
historyRamSizeLog2 = 10, historyRamSizeLog2 = 10,
catchAccessFault = true, catchAccessFault = true,
compressedGen = false, compressedGen = true,
busLatencyMin = 1, busLatencyMin = 1,
injectorStage = true injectorStage = true
), ),

22
src/main/scala/vexriscv/demo/SynthesisBench.scala
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@ -101,22 +101,22 @@ object VexRiscvSynthesisBench {
} }
// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full) val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache, fullNoMmuNoCache, noCacheNoMmuMaxPerf, fullNoMmuMaxPerf, fullNoMmu, full)
// val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache) // val rtls = List(smallestNoCsr, smallest, smallAndProductive, smallAndProductiveWithICache)
// val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full)
val rtls = List(fullNoMmu) // val rtls = List(fullNoMmu)
// val targets = XilinxStdTargets(
// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
// ) ++ AlteraStdTargets(
// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
// ) ++ IcestormStdTargets().take(1)
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ) ++ AlteraStdTargets(
quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
) ++ IcestormStdTargets().take(1)
// val targets = XilinxStdTargets(
// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
// )
// val targets = AlteraStdTargets( // val targets = AlteraStdTargets(
// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", // quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",

9
src/test/scala/vexriscv/TestIndividualFeatures.scala
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@ -268,8 +268,7 @@ class IBusDimension extends VexRiscvDimension("IBus") {
val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL) val catchAll = universes.contains(VexRiscvUniverse.CATCH_ALL)
val cmdForkOnSecondStage = r.nextBoolean() val cmdForkOnSecondStage = r.nextBoolean()
val cmdForkPersistence = r.nextBoolean() val cmdForkPersistence = r.nextBoolean()
val relaxedBusCmdValid = false // r.nextBoolean() && relaxedPcCalculation && prediction != DYNAMIC_TARGET new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{
new VexRiscvPosition("Simple" + latency + (if(cmdForkOnSecondStage) "S2" else "") + (if(cmdForkPersistence) "P" else "") + (if(relaxedBusCmdValid) "Valid" else "") + (if(injectorStage) "InjStage" else "") + (if(compressed) "Rvc" else "") + prediction.getClass.getTypeName().replace("$","")) with InstructionAnticipatedPosition{
override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "") override def testParam = "IBUS=SIMPLE" + (if(compressed) " COMPRESSED=yes" else "")
override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin( override def applyOn(config: VexRiscvConfig): Unit = config.plugins += new IBusSimplePlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
@ -523,9 +522,9 @@ class TestIndividualFeatures extends FunSuite {
// val seed = -2412372746600605141l // val seed = -2412372746600605141l
// val testId = Some(mutable.HashSet[Int](6,11,31,32,53,55,56,64,82)) // val testId = Some(mutable.HashSet[Int](0,28,45,93))
// val testId = Some(mutable.HashSet[Int](31)) // val testId = Some(mutable.HashSet[Int](0))
// val seed = 971825313472546699l // val seed = 2094440864560126345l