Add trace option to regresion
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5e9da0f27a
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fc1bb7249a
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@ -165,15 +165,21 @@ public:
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virtual void checks(){}
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virtual void pass(){ throw success();}
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virtual void fail(){ throw std::exception();}
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void dump(long i){
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#ifdef TRACE
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tfp->dump(i);
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#endif
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}
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Workspace* run(uint32_t timeout = 5000){
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// cout << "Start " << name << endl;
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currentTime = 4;
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// init trace dump
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Verilated::traceEverOn(true);
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#ifdef TRACE
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VerilatedVcdC* tfp = new VerilatedVcdC;
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top->trace(tfp, 99);
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tfp->open((string(name)+ ".vcd").c_str());
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#endif
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// Reset
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top->clk = 0;
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@ -183,7 +189,7 @@ public:
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top->eval(); currentTime = 3;
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top->reset = 1;
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top->eval();
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tfp->dump(0);
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dump(0);
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top->reset = 0;
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top->eval(); currentTime = 2;
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top->clk = 1;
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@ -258,7 +264,7 @@ public:
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// dump variables into VCD file and toggle clock
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for (uint32_t clk = 0; clk < 2; clk++) {
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tfp->dump(i+ clk);
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dump(i+ clk);
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top->clk = !top->clk;
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top->eval();
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@ -291,9 +297,11 @@ public:
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tfp->dump(i);
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tfp->dump(i+1);
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dump(i);
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dump(i+1);
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#ifdef TRACE
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tfp->close();
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#endif
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return this;
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}
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};
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@ -1,8 +1,15 @@
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TRACE=no
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ifeq ($(TRACE),yes)
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VERILATOR_ARGS += --trace
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ADDCFLAGS += -DTRACE
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endif
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run: compile
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./obj_dir/VVexRiscv
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verilate:
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verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 --gdbbt --trace -Wno-WIDTH --x-assign unique --exe main.cpp
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verilator -cc ../../../../VexRiscv.v -O3 -CFLAGS -std=c++11 ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
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compile: verilate
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make -j -C obj_dir/ -f VVexRiscv.mk VVexRiscv
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