A FPGA friendly 32 bit RISC-V CPU implementation
Go to file
Charles Papon fc1bb7249a Add trace option to regresion 2017-03-18 14:06:42 +01:00
project boot 2017-03-08 22:17:48 +01:00
src Add trace option to regresion 2017-03-18 14:06:42 +01:00
.gitignore Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
README.md boot 2017-03-08 22:17:48 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00

README.md

WIP