Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function
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@ -491,7 +491,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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val historyWrite = history.writePort
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val historyWrite = history.writePort
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val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
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val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
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val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2)
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val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
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//Avoid stoping instruction fetch in the middle patch
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//Avoid stoping instruction fetch in the middle patch
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if(compressedGen && cmdToRspStageCount == 1){
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if(compressedGen && cmdToRspStageCount == 1){
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@ -561,6 +561,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
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}
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}
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historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
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historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
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}
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}
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}
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}
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}
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}
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