Fix DynamicPrediction with RVC missprediction between ret instruction and first instruction of the next function

This commit is contained in:
Dolu1990 2018-06-04 19:45:15 +02:00
parent 9f0387350b
commit fc835f370e
1 changed files with 2 additions and 1 deletions

View File

@ -491,7 +491,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val historyWrite = history.writePort
val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2)
val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))
//Avoid stoping instruction fetch in the middle patch
if(compressedGen && cmdToRspStageCount == 1){
@ -561,6 +561,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
}
historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
}
}
}